5.1.2 Double-Gate CNT-FET

To suppress the ambipolar behavior of CNT-FETs and improve the performance of these devices, we propose a double-gate structure as shown in Fig. 5.4. The first gate controls the carrier injection at the source contact, which determines the on-current, and the second one controls the carrier injection at the drain contact, which determines the off-current.

If the drain voltage is applied to the second gate, at any drain voltage the band edge profile near the drain will be nearly flat, as shown in Fig. 5.5-b. In consequence the parasitic tunneling current of holes is suppressed and the parasitic current is limited to thermionic emission of holes over the drain-sided SCHOTTKY barrier.

By applying a voltage higher than the maximum drain voltage to the second gate, thermionic emission of holes over the drain-sided barrier decreases exponentially and consequently a lower off-current is achieved (Fig. 5.5). It should be noted that if the drain voltage reaches a value higher than the second gate voltage, parasitic hole current will increase again.

The output characteristics of the double-gate structure is shown in Fig. 5.6-a. If the second gate is biased at the drain voltage, the drain current will not increase until the drain voltage reaches the first gate voltage. The reason for this behavior is that carriers in the channel see a thick barrier near the drain contact until the drain voltage reaches a value higher than the first gate voltage (see Fig. 5.6-b). If the second gate is biased at a voltage higher than the maximum drain voltage, carries in the channel face a thin barrier even at low drain voltages while the holes barrier at the drain contact is thick.

It is of advantage to apply the drain voltage to the second gate, because parasitic capacitances between the second gate and the drain are avoided, no separate voltage source for the second gate is needed, and the fabrication is more feasible. The off-current is determined by the thermionic emission current over the SCHOTTKY barrier. The drain current, however, is small until the drain voltage reaches a value higher than the first gate voltage. By applying a voltage higher than the maximum drain voltage to the second gate, a high  $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio can be obtained.

Figure 5.4: Sketch of the double-gate (DG) structure.

Regarding the separation between the two gates several parameters should be considered: By decreasing this separation, the parasitic capacitance between the gates increases which deteriorates the frequency response of the device. Also because of the narrow band gap of CNTs, at certain operating voltages the band to band tunneling current will increase by decreasing this distance, which affects the off-current.

Figure 5.5: a) Comparison of the transfer characteristics of the single-gate (SG) and double-gate (DG) structure at $V_\textrm {D}$= 0.6 V. Two different biases are assumed for the second gate. b) Comparison of the band edges profile, along the SG and DG structure. $T_\textrm {Ins}$=4 nm and $L_\textrm {GS}$= $L_\textrm {GD}$=2 nm.

Figure 5.6: a) Output characteristics of the double-gate (DG) structure. b) Conduction band edge profile of the DG structure at low drain biases.

M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors