To cope with the requirements of careful house holding with memory and CPU time requirements algorithmic optimization is necessary for the surface representation and movement, regardless of the type of the applied algorithm. It has not to be noted that this fact is of special importance for three-dimensional simulations.
Three-dimensional effects are gaining more and more importance in devices as well as in interconnects and require a physically based geometry generation of the structures used as input for the interconnect and device simulations. Therefore topography simulation is preferably connected to ECAD and layout tools, including lithography. The necessary level of accuracy has to be checked carefully. New planarization techniques allow planar layer approaches for some of the layers. For the other, non-planar layers it has to be questioned whether phenomenological schemes like isotropic or anisotropic models are sufficient or whether more detailed and more time consuming modeling of the involved deposition and etching technologies is necessary and justified.
Modeling of many etching and deposition steps, e.g., plasma etch, chemical vapor deposition (CVD), and chemical mechanical planarization (CMP) is limited by the lack of knowledge of the physical and chemical surface processes. Selection of reactions and rate coefficients is critical to make predictions on deposited and etched profiles. Detailed knowledge about the fundamental reaction mechanisms of single process steps is still missing for numerous physical, chemical and plasma processes. The challenge of understanding ion surface interactions must be met for predictive modeling of plasma enhanced techniques. Simulation assists in testing which effects contribute most to the explanation of newly observed phenomena not yet fully understood. Many most recently developed thin film and etching techniques work very fine at an empirical, engineering base but still lack full understanding of what are the most decisive parameters. Theories therefor ensure going the right direction for future optimization needed for pushing these processes to their application limit. New theories and most recent results from detailed studies of surface interaction at a very high physically and chemically based level also have to be revised for applicability within feature scale topography simulation. Simulation, going hand-in-hand with the validation of new theoretical cognition allows further improvement of existing techniques in order to warrant conformal and void-free filling of features with continuously increasing aspect ratios.
Together with the development of new processes like advanced fill techniques, new materials are emerging into semiconductor fabrication: copper and low dielectrics are considered to complement conventional // and technologies. Copper requires new barrier materials like Tantalum and low materials reduced from complex organic molecules need new considerations about the gas phase chemistry involved in the processes. The same applies to high, low leakage materials under discussion for gate and capacitance dielectrics, which are needed in order to keep DRAM capacitances high enough despite ever shrinking trench capacitor sizes. Additional barrier materials such as TaSiN, WN, WSiN, etc., may also find broad application. The list of new materials is completed with nitrides and oxynitrides as alternative to oxides and perfluorocompound (PFC) chemistries for etching processes. Modeling of the process technology for new materials -- to some part quite similar to existing materials, requiring only parameter tuning, to some part based on completely different fundamentals -- has to be comprehensive enough to provide frameworks for addressing phenomena affiliated with these new materials.
The increasing wafer size, ranging up to 300mm and still going up, represents new challenges for maintaining the uniformity of the processes from wafer-to-wafer as well as within-wafer. Yield and quality issues force new developments in modeling and simulation in order to make provisions to estimate the variations in sputter profiles and void formation at different positions on the wafer.
Finally integration of reactor- and feature scale simulation has to provide the process engineer with means to quickly investigate the influence of process parameters on the final structure of the device. Ideally this integration is formulated in a way of easy accessibility to tell the engineer quickly and understandably, which controller he has to turn in order to improve his devices or in order to get back into the specification limits of the process.
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