Defining the gate and the gate recess the following quantities are subject to statistical process variations. Any vertical layer depth of the underlying MBE layer sequence can be controlled to sub nm precision during MBE growth. The most critical thicknesses during the semiconductor process are those defined by etching, so this technique is addressed. As reported e.g in [79,239] wet etching is subject to surface wetting problems in small recesses which reduce uniformity of the devices on a wafer. The gate-to-channel separation and the recess geometry are affected by this uncertainty. Dry etching can improve the uniformity, however reactive ion etching (RIE) introduces subsurface damage which can be critical due to the processing close to the conducting channel [46,239]. Inductively coupled plasma etching has been developed to achieve both uniformity and damage controlled etching  on the industrial scale. The uncertainty affects all those geometry quantities which are not controlled by a highly selective etch stop layer. This includes the lateral etching and the etch depth additional recesses. The lateral lengths, however are defined by either optical stepper alignment or the alignment of additional masks where the precision again depends on the accuracy of the stepper.