SIESTA (Simulation Environment for Semiconductor Technology Analysis) was particularly designed to overcome these limitations. Its open simulation tool interface enables the modeling of simulation problems with virtually arbitrary simulation tools. Moreover, SIESTA offers abstractions which keep simulation models manageable, and reduce the administrative effort to minimal levels. These abstractions allow to design simulation models which represent a couple of device categories of a fabrication technology, rather than just a single device. Additionally, SIESTA offers a strong support for a comprehensive calibration of simulation models, and it provides services for a rigorous TCAD based optimization of a fabrication technology and its electronic devices.
Historically, SIESTA stems from the VISTA/SFC TCAD environment , which served as a prototype in many respects during the development of SIESTA. Many ideas of VISTA/SFC have been adopted and refined. In contrast to the implementation of VISTA/SFC, which did not benefit from a prototype implementation itself, it was possible to implement SIESTA in a top-down manner which led to a slim and clearly structured software.