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Abstract

Down-scaling of integrated circuits to the deep sub-micron regime increases the influence of interconnects on circuit behavior. As devices are getting faster and line widths get smaller parasitic effects of the interconnects become the limiting factor for further improvements in circuit speed. With clock frequencies in the GHz regime, integrated circuits will behave more and more like microwave circuits.

During the design phase care must be taken on various parasitic effects, like attenuation caused by resistive voltage drops, self-heating due to losses, delay times, crosstalk (caused by capacitive or inductive coupling or by the substrate), reflections incurred by discontinuities, skin-effect and eddy currents (e.g. in on-chip spiral inductors). While it is important to consider the inductive effects of very long interconnects with low resistance and of course on-chip inductors, the electrical characteristics of local interconnects lines is mainly determined by their resistance and capacitance. With the introduction of new materials (Copper, low-k dielectrics) parasitic effects can be reduced to a certain degree, but not eliminated. Therefore highly accurate models are required especially for designs with reduced safety margins close to the physical limits.

In this thesis a set of simulation tools for highly accurate extraction of parasitic capacitances and resistances, simulation of transient electric behavior, and investigation of the thermal characteristics has been developed. Special attention has been directed to an efficient implementation considering both runtime and memory consumption. Compared to other (commercial) tools the simulator presented in this work has the ability to perform calculations with anisotropic dielectric materials and coupled electro-thermal simulations with temperature-dependent material properties. The finite element method (FEM) is used for the numeric solution of the partial differential equations. This method has been selected over other methods because of its numerical robustness and the applicability to all involved equation types. For the discretization of the time domain both the backward Euler and the trapezoid method (Crank-Nicolson) have been implemented. The spatial discretization is carried out with the Galerkin method. The discretization results in a linear system of equations which is stored in a compressed sparse matrix format for efficient usage of main memory. The equation system is solved with a preconditioned conjugate gradient solver (ICCG). Some of the involved partial differential equations exhibit a slight non-linear behavior. For that reason a simple relaxation technique is used to find the solution.

For highly accurate simulations it is essential to model the simulation domain geometrically as exact as possible. Therefor the boundary representation is used, where solids are formed by their polygonal hull. Adjacent solids must not overlap and must have conformal faces, lines, and points. Because of these consistency requirements a manual geometry construction is nearly impossible. For this reason a preprocessor has been developed, which allows a layer-based geometry construction and enforces the required consistency with a solid modeling technique.

The accuracy and efficiency of a finite element simulation depends strongly on the quality of the simulation grid. The layered structure of the geometry can be utilized for a simple but robust grid generation method. Pros and cons of this method will be discussed by a comparison with other gridding techniques.

The simulators extract not only global parameters like resistances and capacitances, also distributed quantities like potential, temperature, or current density are calculated. To display these three-dimensional scalar and vector fields a visualization program has been developed, which allows for the representation of the quantity on the surface, generation of contour lines and faces, cuts, and the calculation of streamlines.

Finally four application examples are presented to demonstrate the capabilities of the simulation tools. An electro-thermal simulation is performed for an Al-line test structure and the results are compared with experimentally measured values. The electrical and thermal behavior of an interconnect line with a notch (e.g. caused by electromigration) is investigated in detail. The resistance of vias in a Cu dual damascene architecture is calculated, and delay times and cross-talk in a matched poly-resistor pair are computed with a transient simulation run.


next up previous contents
Next: Danksagung Up: Dissertation Rainer Sabelka Previous: Kurzfassung

R. Sabelka: Dreidimensionale Finite Elemente Simulation von Verdrahtungsstrukturen auf Integrierten Schaltungen