2.7.1 Basic Process

Ultra-Low-Power process technology is essentially the same as a high-performance CMOS technology (see Section A.4.2) with a few modifications which result in a number of also technological advantages:

1.

In a high-performance ULP process the threshold voltage is very small (about 80mV), but not zero (see Sections 6.5 and E.1).

2.

The source/drain extensions are heavily doped to improve on performance. An LDD is not necessary because hot-carrier degradation is virtually precluded.

3.

The deep source/drain implants can be omitted in ULP technologies with optimum energy efficiency and moderate performance. Instead, only the shallow source/drain implant is used, which reduces the process complexity.

4.

No precautions against latch-up (cf. [36]) are required because this phenomenon is precluded at $\ensuremath{V_{\mathit{DD}}}\xspace <\rm 1.5V$ when the wells are routed properly.

5.

The channel profile can be chosen more freely in comparison to that of high-voltage technologies, because the DIBL effect is reduced. However, short-channel effects, which require roughly the same counter-measures, are still present. Therefore, a reduction of much below one volt does not really help in this respect.

6.

As the optimum choice of depends essentially on the circuit activity, devices with different threshold voltages on the same chip (multiple-threshold technique) will be used in heterogeneous systems such as SRAMs or microprocessors (low for the processor core and high for the cache memory).

7.

As the drive current is only about 0.1mA in moderate-performance technologies the problem of electromigration is largely reduced.

8.

The gate oxide (or the equivalent gate insulator) is made very thin so as to reach the tunneling-current limit. Ultra-thin gate oxides and oxinitrides have long been under investigation [48,49,39,52] and are optimal for low-voltage operation, albeit at some gate tunneling leakage. It turns out that the reliability of ultra-thin oxides can be higher than that of conventional thin oxides ( $\ensuremath{t_{\mathit{ox}}}\xspace >\rm 6nm$) and that the hot-carrier degradation is reduced by the higher direct-tunneling probability.

While all points listed above would mean fairly radical changes to conventional high-voltage processes (with in the range of 3.3 to 5V) the differences to future deep-sub-micron technology generations as projected by the SIA [4] are not as large. This indicates some convergence of high-performance and Ultra-Low-Power CMOS technologies.