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6.2 Simulation of a SiGe Heterojunction Bipolar Transistor

The investigated $ 0.4 \times 12\,\mu$m$ ^2$ SiGe-HBT device structure is obtained by process simulation [110], see Figure 6.4. For DC simulations usually only the active part (base and emitter area, collector contact moved to the bottom) of the device is required. For that reason the collector area was cut to speed-up the simulations. Only half of the real structure was simulated because of symmetry. The upper figure in Figure 6.7 shows a comparison of simulated and measured forward Gummel plots at $ \ensuremath{V_\mathrm{CE}}= 1\,$V.

Figure 6.4: Active antimony concentration of the investigated SiGe Heterojunction Bipolar Transistor (large device).
\includegraphics[height=8.0cm]{figures/siger.eps}

For AC simulations, however, it is absolutely necessary to take the complete device structure into account. Otherwise, the simulation of the reduced device structure cannot reproduce the important capacitances between collector and substrate $ C_\mathrm{CS}$ as well as between base and collector $ C_\mathrm{BC}$. In addition, the correct base and collector resistances are missing. There are two possibilities to overcome this problem. Either the missing parts are approximated by introducing linear elements in a post-processing step or a larger or even complete structure is used for AC simulations. The first option allows faster simulations but gives approximated results. The second one produces more accurate results and does not require a post-processing step, but takes much more time: in the example the computational effort of device simulation is 2.5 times higher.

In Figure 6.6 both options are compared: in the frequency range between 50$ \,$MHz and 31$ \,$GHz measured and simulated S-parameters at $ \ensuremath{V_\mathrm{CE}}= $1$ \,$V and current densities $ {\ensuremath{J_\mathrm{C}}} = 28\,$kA/cm$ ^2$ and $ {\ensuremath{J_\mathrm{C}}} = 76\,$kA/cm$ ^2$ are shown in the frequency range between 50$ \,$MHz and 31$ \,$GHz. For the first option the device structure is embedded in a circuit containing the following elements: $ C_\mathrm{CS} = $50$ \,$fF, $ C_\mathrm{BC} = $20$ \,$fF, $ R_\mathrm{B} =
$15$ \,\Omega$ and $ R_\mathrm{C} = $27$ \,\Omega$. Their values were experimentally estimated. The results of the second option are the intrinsic parameters only.

For the same device the matched gain $ g_\mathrm{m}$ and the short-circuit current gain $ \underline{H_{21}}$ is calculated in order to extract the figures of merit cut-off frequency $ f_\textrm {T}$ and the maximum oscillation frequency $ f_\mathrm{max}$ found at the intersection with the $ 0\,$dB line (unity gain point). 6.7 shows the comparison of the simulation results and the corresponding measurement data. While the measurement data ends at $ 31\,$GHz the simulation could be extended to frequencies beyond this intersection. Note that the peak $ f_\textrm {T}$ in the left figure of Figure 6.7 corresponds exactly to the frequency at the respective intersection in the right figure.

Figure 6.7 shows also the effect of the introduction of an anisotropic electron mobility [160]. In addition, results obtained by the commercial device simulator DESSIS [111] using default models and parameters are included for comparison. The agreement in order of the typical curve characteristics with measured and transformed data proves the efficiency of the approach. In addition, the performance speed-up in comparison to alternatives is an important advantage. However, a general approach to match simulated results and measured data perfectly has to comprise a proper physical modeling of the complete device since there are no extrinsic fitting parameters available.

Figure 6.5: Comparison of simulated and measured forward Gummel plots at $ V_\textrm {CE}= 1\ $V.
Figure 6.6: The figures compare S-parameters in a combined Smith/polar chart with a radius of one from $ 50\ $MHz to $ 31\ $GHz at $ \ensuremath{V_\mathrm{CE}}= 1\ $V for $ {\ensuremath{J_\mathrm{C}}} = 28\,$kA/cm$ ^2$ (left) and $ {\ensuremath{J_\mathrm{C}}} = 76\,$kA/cm$ ^2$ (right) for a large device structure and a small one embedded in a circuit.
Figure 6.7: The cut-off frequency $ f_\textrm {T}$ versus collector current $ I_\mathrm{C}$ at $ {V_\textrm {CE}} = 1\ $V (left) and the short-circuit current gain versus frequency (right) is depicted [233].

\includegraphics[width=0.47\linewidth]{figures/ams_dc.eps} \includegraphics[width=0.47\linewidth]{figures/ams_sparam1.eps} \includegraphics[width=0.47\linewidth]{figures/ams_sparam2.eps}
\includegraphics[width=0.47\linewidth]{figures/ams_ft.eps} \includegraphics[width=0.47\linewidth]{figures/ams_h21gm.eps}


next up previous contents
Next: 6.3 Simulation of a Up: 6. Examples Previous: 6.1 Simulation of an

S. Wagner: Small-Signal Device and Circuit Simulation