Publications Helmut Puchner

36 records

Publications in Scientific Journals

8.   Sheikholeslami, A., Parhami, F., Puchner, H., Selberherr, S. (2007).
Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers.
Journal of Physics: Conference Series, 61, 1051–1055. https://doi.org/10.1088/1742-6596/61/1/208 (reposiTUm)

7.  C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr:
"Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process";
IEEE Transactions on Electron Devices, 51 (2004), 7; 1129 - 1134. https://doi.org/10.1109/TED.2004.829868

6.  A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, S. Selberherr:
"Simulation of Void Formation in Interconnect Lines";
Proceedings of SPIE, 5117 (2003), 445 - 452. https://doi.org/10.1117/12.498783

5.  V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr:
"A Methodology for Deep Sub-0.25µm CMOS Technology Prediction";
IEEE Transactions on Electron Devices, 48 (2001), 10; 2331 - 2336. https://doi.org/10.1109/16.954473

4.  H. Puchner, R. Castagnetti, W. Pyka:
"Minimizing Thick Resist Sidewall Slope Dependence on Design Geometry by Optimizing Bake Conditions";
Microelectronic Engineering, 53 (2000), 429 - 432.

3.   Puchner, H., Selberherr, S. (1995).
An Advanced Model for Dopant Diffusion in Polysilicon.
IEEE Transactions on Electron Devices, 42(10), 1750–1755. https://doi.org/10.1109/16.464423 (reposiTUm)

2.   Stippel, H., Leitner, E., Pichler, Ch., Puchner, H., Strasser, E., Selberherr, S. (1995).
Process Simulation for the 1990s.
Microelectronics Journal, 26(2–3), 203–215. https://doi.org/10.1016/0026-2692(95)98922-e (reposiTUm)

1.   Halama, S., Fasching, F., Fischer, C., Kosina, H., Leitner, E., Lindorfer, P., Pichler, Ch., Pimingstorfer, H., Puchner, H., Rieger, G., Schrom, G., Simlinger, T., Stiftinger, M., Stippel, H., Strasser, E., Tuppa, W., Wimmer, K., Selberherr, S. (1995).
The Viennese Integrated System for Technology CAD Applications.
Microelectronics Journal, 26(2–3), 137–158. https://doi.org/10.1016/0026-2692(95)98918-h (reposiTUm)

Talks and Poster Presentations (with Proceedings-Entry)

23.   Sheikholeslami, A., Heinzl, R., Holzer, S., Heitzinger, C., Spevak, M., Leicht, M., Häberlen, O., Fugger, J., Badrieh, F., Parhami, F., Puchner, H., Grasser, T., Selberherr, S. (2006).
Applications of Two- And Three-Dimensional General Topography Simulator in Semiconductor Manufacturing Processes.
In Proceedings of the 14th Iranian Conference on Electrical Engineering ICEE 2006 (p. 4), Tehran. (reposiTUm)

22.   Wittmann, R., Puchner, H., Ceric, H., Selberherr, S. (2006).
Impact of Random Bit Values on NBTI Lifetime of an SRAM Cell.
In Proceedings 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 41–44), Singapore. (reposiTUm)

21.   Sheikholeslami, A., Selberherr, S., Parhami, F., Puchner, H. (2006).
Planarization of Passivation Layers During Manufacturing Processes of Image Sensors.
In Proceedings of the 6th International Conference on Numerical Simulation of Optoelectronic Devices (pp. 35–36), Singapore. (reposiTUm)

20.   Sheikholeslami, A., Parhami, F., Puchner, H., Selberherr, S. (2006).
Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers.
In International Conference on Nanoscience and Technology (ICNT 2006) (pp. 163–164), Basel. (reposiTUm)

19.   Sheikholeslami, A., Parhami, F., Heinzl, R., Al-Ani, E., Heitzinger, C., Badrieh, F., Puchner, H., Grasser, T., Selberherr, S. (2005).
Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines.
In 2005 International Conference On Simulation of Semiconductor Processes and Devices, Tokyo, Japan. https://doi.org/10.1109/sispad.2005.201504 (reposiTUm)

18.   Wittmann, R., Puchner, H., Hinh, L., Ceric, H., Gehring, A., Selberherr, S. (2005).
Impact of NBTI-driven Parameter Degradation on Lifetime of a 90nm P-Mosfet.
In Final Report of the IEEE International Integrated Reliability Workshop (IIRW) (pp. 99–102), S. Lake Tahoe. (reposiTUm)

17.   Sheikholeslami, A., Al-Ani, E., Heinzl, R., Heitzinger, C., Parhami, F., Badrieh, F., Puchner, H., Grasser, T., Selberherr, S. (2005).
Level Set Method Based General Topography Simulator and Its Application in Interconnect Processes.
In ULIS 2005 6th International Conference on Ultimate Integration of Silicon (pp. 139–142), Bologna, Austria. (reposiTUm)

16.   Wittmann, R., Puchner, H., Hinh, L., Ceric, H., Gehring, A., Selberherr, S. (2005).
Simulation of Dynamic NBTI Degradation for a 90 Nm CMOS Technology.
In NSTI Nanotech Technical Proceedings (pp. 29–32), Anaheim, Austria. (reposiTUm)

15.  A. Sheikholeslami, C. Heitzinger, F. Badrieh, H. Puchner, S. Selberherr:
"Three-Dimensional Topography Simulation Based on a Level Set Method";
Talk: International Spring Seminar on Electronics Technology (ISSE), Sofia; 2004-05-13 - 2004-05-16; in: "Proceedings IEEE International Spring Seminar on Electronics Technology 27th ISSE 2004", IEEE, 2 (2004), ISBN: 0-7803-8422-9; 263 - 265.

14.  A. Sheikholeslami, C. Heitzinger, S. Selberherr, F. Badrieh, H. Puchner:
"Capacitances in the Backend of a 100nm CMOS Process and their Predictive Simulation";
Poster: Informationstagung Mikroelektronik (ME), Wien; 2003-10-01 - 2003-10-02; in: "Beiträge der Informationstagung Mikroelektronik 2003", (2003), ISBN: 3-85133-030-7; 481 - 486.

13.  C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr:
"Feature Scale Simulation of Advanced Etching Processes";
Talk: Meeting of the Electrochemical Society, Physical Electrochemistry, Orlando; 2003-10-12 - 2003-10-16; in: "204th ECS Meeting", (2003), ISBN: 1-56677-398-9; 1259.

12.  F. Badrieh, H. Puchner, C. Heitzinger, A. Sheikholeslami, S. Selberherr:
"From Feature Scale Simulation to Backend Simulation for a 100nm CMOS Process";
Poster: European Solid-State Device Research Conference (ESSDERC), Estoril; 2003-09-16 - 2003-09-18; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2003), ISBN: 0-7803-7999-3; 441 - 444.

11.  C. Heitzinger, A. Sheikholeslami, H. Puchner, S. Selberherr:
"Predictive Simulation of Void Formation During the Deposition of Silicon Nitride and Silicon Dioxide Films";
Talk: Meeting of the Electrochemical Society (ECS), Paris; 2003-04-26 - 2003-05-02; in: "203rd ECS Meeting", (2003), ISBN: 1-56677-347-4; 356 - 365.

10.  V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr:
"A Methodology for Deep Sub-Quartermicron CMOS Technology Characterization";
Poster: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Athens, Greece; 2001-09-05 - 2001-09-07; in: "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)", (2001), ISBN: 3-211-83708-6; 428 - 431. https://doi.org/10.1007/978-3-7091-6244-6_99

9.  T. Grasser, H. Kosina, M. Gritsch, S. Selberherr, H. Puchner, S. Aronowitz:
"Accurate Simulation of Substrate Currents by Accounting for the Hot Electron Tail Population";
Talk: European Solid-State Device Research Conference (ESSDERC), Nürnberg; 2001-09-11 - 2001-09-13; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2001), ISBN: 2-914601-01-8; 215 - 218.

8.  V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr:
"Reliable Prediction of Deep Sub-Quartermicron CMOS Technology Performance";
Talk: IEEE Conference on Nanotechnology (NANO), Maui; 2001-10-28 - 2001-10-30; in: "Proceedings of the IEEE Conference on Nanotechnology (NANO)", (2001), ISBN: 0-7803-7215-8; 201 - 206. https://doi.org/10.1109/NANO.2001.966419

7.  H. Puchner, P. Neary, S. Aronowitz, S. Selberherr:
"A Transient Activation Model for Phosphorus after Sub-Amorphizing Channeling Implants";
Talk: European Solid-State Device Research Conference (ESSDERC), Bologna; 1996-09-09 - 1996-09-11; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (1996), ISBN: 2-86332-196-x; 157 - 160.

6.   Puchner, H., Selberherr, S. (1995).
A Two-Dimensional Dopant Diffusion Model for Polysilicon.
In Abstracts Meeting on Impurity Diffusion and Defects in Silicon and Related Materials (pp. 16–17), Athen, Austria. (reposiTUm)

5.   Puchner, H., Selberherr, S. (1995).
Simulation of Ion Implantation Using the Four-Parameter Kappa Distribution Function.
In Proceedings Solid-State and Integrated-Circuit Technology Conference (pp. 295–297), Peking, Austria. (reposiTUm)

4.  H. Puchner, S. Selberherr:
"An Advanced Model for Dopant Diffusion in Polysilicon";
Talk: Conference on Emerging Issues in Mathematics and Computation from the Materials Sciences, Pittsburgh; 1994-04-18 - 1994-04-20; in: "Abstracts Conference on Emerging Issues in Mathematics and Computation from the Materials Sciences", (1994), A13.

3.   Puchner, H., Selberherr, S. (1994).
Dynamic Grain-Growth and Static Clustering Effects on Dopant Diffusion in Polysilicon.
In Proceedings NUPAD V, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits (pp. 109–112), Honolulu, Austria. (reposiTUm)

2.  H. Puchner, S. Selberherr:
"Simulation of Graft Base Formation and Emitter Outdiffusion in High-Performance Bipolar LSIs";
Talk: European Solid-State Device Research Conference (ESSDERC), Edinburgh; 1994-09-11 - 1994-09-15; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (1994), ISBN: 2-86332-157-9; 165 - 168.

1.   Halama, S., Fasching, F., Fischer, C., Kosina, H., Leitner, E., Pichler, C., Pimingstorfer, H., Puchner, H., Rieger, G., Schrom, G., Simlinger, T., Stiftinger, M., Stippel, H., Strasser, E., Tuppa, W., Wimmer, K., Selberherr, S. (1993).
The Viennese Integrated System for Technology CAD Applications.
In Technology CAD Systems (pp. 197–236), Wien, Austria. https://doi.org/10.1007/978-3-7091-9315-0_10 (reposiTUm)

Talks and Poster Presentations (without Proceedings-Entry)

1.   Sheikholeslami, A., Heitzinger, C., Puchner, H., Badrieh, F., Selberherr, S. (2003).
Simulation of Void Formation in Interconnect Lines.
SPIE VLSI Circuits and Systems, Sevilla, Spain, Austria. (reposiTUm)

Habilitation Theses

1.   Puchner, H. (2001).
Process Integration for Deep-Submicron CMOS Technology
Technische Universität Wien. (reposiTUm)

Doctor's Theses (authored and supervised)

1.  H. Puchner:
"Advanced Process Modeling for VLSI Technology";
Supervisor, Reviewer: S. Selberherr, W. Fallmann; Institut für Mikroelektronik, 1996; oral examination: 1996-05-31.

Scientific Reports

2.   Martins, R., Puchner, H., Selberherr, S., Simlinger, T., Tuppa, W. (1996).
VISTA Status Report June 1996.
(reposiTUm)

1.   Mlekus, R., Pichler, C., Puchner, H., Selberherr, S., Tuppa, W. (1995).
VISTA Status Report June 1995.
(reposiTUm)