Publications Helmut Puchner
30 records
| 7. | C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr: "Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process"; IEEE Transactions on Electron Devices, 51, (2004), 1129 - 1134 doi:10.1109/TED.2004.829868. BibTeX |
| 6. | A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, S. Selberherr: "Simulation of Void Formation in Interconnect Lines"; Proceedings of SPIE, 5117, (2003), 445 - 452 doi:10.1117/12.498783. BibTeX |
| 5. | V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr: "A Methodology for Deep Sub-0.25µm CMOS Technology Prediction"; IEEE Transactions on Electron Devices, 48, (2001), 2331 - 2336 doi:10.1109/16.954473. BibTeX |
| 4. | H. Puchner, R. Castagnetti, W. Pyka: "Minimizing Thick Resist Sidewall Slope Dependence on Design Geometry by Optimizing Bake Conditions"; Microelectronic Engineering, 53, (2000), 429 - 432. BibTeX |
| 3. | S. Halama, F. Fasching, C. Fischer, H. Kosina, E. Leitner, P. Lindorfer, C. Pichler, H. Pimingstorfer, H. Puchner, G. Rieger, G. Schrom, T. Simlinger, M. Stiftinger, H. Stippel, E. Strasser, W. Tuppa, K. Wimmer, S. Selberherr: "The Viennese Integrated System for Technology CAD Applications"; Microelectronics Journal, 26, (1995), 137 - 158 doi:10.1016/0026-2692(95)98918-H. BibTeX |
| 2. | H. Puchner, S. Selberherr: "An Advanced Model for Dopant Diffusion in Polysilicon"; IEEE Transactions on Electron Devices, 42, (1995), 1750 - 1755 doi:10.1109/16.464423. BibTeX |
| 1. | H. Stippel, E. Leitner, C. Pichler, H. Puchner, E. Strasser, S. Selberherr: "Process Simulation for the 1990s"; Microelectronics Journal, 26, (invited) (1995), 203 - 215 doi:10.1016/0026-2692(95)98922-E. BibTeX |
| 18. | A. Sheikholeslami, F. Parhami, R. Heinzl, E. Al-Ani, C. Heitzinger, F. Badrieh, H. Puchner, T. Grasser, S. Selberherr: "Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines"; Poster: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Tokyo, Japan; 2005-09-01 - 2005-09-03; in "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)", (2005), ISBN: 4-9902762-0-5, 187 - 190 doi:10.1109/SISPAD.2005.201504. BibTeX |
| 17. | R. Wittmann, H. Puchner, L. Hinh, H. Ceric, A. Gehring, S. Selberherr: "Simulation of Dynamic NBTI Degradation for a 90 nm CMOS Technology"; Talk: The Nanotechnology Conference and Trade Show, Anaheim; 2005-05-08 - 2005-05-12; in "NSTI Nanotech Technical Proceedings", (2005), Vol. 3 (CDROM ISBN 0-9767985-4-9), ISBN: 0-9767985-2-2, 29 - 32. BibTeX |
| 16. | A. Sheikholeslami, E. Al-Ani, R. Heinzl, C. Heitzinger, F. Parhami, F. Badrieh, H. Puchner, T. Grasser, S. Selberherr: "Level Set Method Based General Topography Simulator and its Application in Interconnect Processes"; Poster: International Conference on Ultimate Integration of Silicon (ULIS), Bologna; 2005-04-07 - 2005-04-08; in "ULIS 2005 6th International Conference on Ultimate Integration of Silicon", (2005), ISBN: 8890084707, 139 - 142. BibTeX |
| 15. | A. Sheikholeslami, C. Heitzinger, F. Badrieh, H. Puchner, S. Selberherr: "Three-Dimensional Topography Simulation Based on a Level Set Method"; Talk: International Spring Seminar on Electronics Technology (ISSE), Sofia; 2004-05-13 - 2004-05-16; in "Proceedings IEEE International Spring Seminar on Electronics Technology 27th ISSE 2004", (2004), 2, ISBN: 0-7803-8422-9, 263 - 265. BibTeX |
| 14. | C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr: "Feature Scale Simulation of Advanced Etching Processes"; Talk: Meeting of the Electrochemical Society, Physical Electrochemistry, Orlando; 2003-10-12 - 2003-10-16; in "204th ECS Meeting", (2003), ISBN: 1-56677-398-9, 1259. BibTeX |
| 13. | A. Sheikholeslami, C. Heitzinger, S. Selberherr, F. Badrieh, H. Puchner: "Capacitances in the Backend of a 100nm CMOS Process and their Predictive Simulation"; Poster: Informationstagung Mikroelektronik (ME), Wien; 2003-10-01 - 2003-10-02; in "Beiträge der Informationstagung Mikroelektronik 2003", (2003), ISBN: 3-85133-030-7, 481 - 486. BibTeX |
| 12. | F. Badrieh, H. Puchner, C. Heitzinger, A. Sheikholeslami, S. Selberherr: "From Feature Scale Simulation to Backend Simulation for a 100nm CMOS Process"; Poster: European Solid-State Device Research Conference (ESSDERC), Estoril; 2003-09-16 - 2003-09-18; in "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2003), ISBN: 0-7803-7999-3, 441 - 444. BibTeX |
| 11. | C. Heitzinger, A. Sheikholeslami, H. Puchner, S. Selberherr: "Predictive Simulation of Void Formation During the Deposition of Silicon Nitride and Silicon Dioxide Films"; Talk: Meeting of the Electrochemical Society (ECS), Paris; 2003-04-26 - 2003-05-02; in "203rd ECS Meeting", (2003), ISBN: 1-56677-347-4, 356 - 365. BibTeX |
| 10. | V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr: "Reliable Prediction of Deep Sub-Quartermicron CMOS Technology Performance"; Talk: IEEE Conference on Nanotechnology (NANO), Maui; 2001-10-28 - 2001-10-30; in "Proceedings of the IEEE Conference on Nanotechnology (NANO)", (2001), ISBN: 0-7803-7215-8, 201 - 206 doi:10.1109/NANO.2001.966419. BibTeX |
| 9. | T. Grasser, H. Kosina, M. Gritsch, S. Selberherr, H. Puchner, S. Aronowitz: "Accurate Simulation of Substrate Currents by Accounting for the Hot Electron Tail Population"; Talk: European Solid-State Device Research Conference (ESSDERC), Nürnberg; 2001-09-11 - 2001-09-13; in "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2001), ISBN: 2-914601-01-8, 215 - 218. BibTeX |
| 8. | V. Palankovski, N. Belova, T. Grasser, H. Puchner, S. Aronowitz, S. Selberherr: "A Methodology for Deep Sub-Quartermicron CMOS Technology Characterization"; Poster: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Athens, Greece; 2001-09-05 - 2001-09-07; in "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)", (2001), ISBN: 3-211-83708-6, 428 - 431 doi:10.1007/978-3-7091-6244-6_99. BibTeX |
| 7. | H. Puchner, P. Neary, S. Aronowitz, S. Selberherr: "A Transient Activation Model for Phosphorus after Sub-Amorphizing Channeling Implants"; Talk: European Solid-State Device Research Conference (ESSDERC), Bologna; 1996-09-09 - 1996-09-11; in "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (1996), ISBN: 2-86332-196-x, 157 - 160. BibTeX |
| 6. | H. Puchner, S. Selberherr: "Simulation of Ion Implantation Using the Four-Parameter Kappa Distribution Function"; Talk: International Conference on Solid State and Integrated Circuit Technology (ICSICT), Peking; 1995-09-24 - 1995-09-28; in "Proceedings Solid-State and Integrated-Circuit Technology Conference", (1995), 295 - 297. BibTeX |
| 5. | H. Puchner, S. Selberherr: "A Two-Dimensional Dopant Diffusion Model for Polysilicon"; Talk: Meeting on Impurity Diffusion and Defects in Silicon and Related Materials, Athen; 1995-05-03 - 1995-05-04; in "Abstracts Meeting on Impurity Diffusion and Defects in Silicon and Related Materials", (1995), 16 - 17. BibTeX |
| 4. | H. Puchner, S. Selberherr: "Simulation of Graft Base Formation and Emitter Outdiffusion in High-Performance Bipolar LSIs"; Talk: European Solid-State Device Research Conference (ESSDERC), Edinburgh; 1994-09-11 - 1994-09-15; in "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (1994), ISBN: 2-86332-157-9, 165 - 168. BibTeX |
| 3. | H. Puchner, S. Selberherr: "Dynamic Grain-Growth and Static Clustering Effects on Dopant Diffusion in Polysilicon"; Talk: International Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits (NUPAD), Honolulu; 1994-06-05 - 1994-06-06; in "Proceedings NUPAD V, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits", (1994), ISBN: 0-7803-1867-6, 109 - 112. BibTeX |
| 2. | H. Puchner, S. Selberherr: "An Advanced Model for Dopant Diffusion in Polysilicon"; Talk: Conference on Emerging Issues in Mathematics and Computation from the Materials Sciences, Pittsburgh; 1994-04-18 - 1994-04-20; in "Abstracts Conference on Emerging Issues in Mathematics and Computation from the Materials Sciences", (1994), A13. BibTeX |
| 1. | S. Halama, F. Fasching, C. Fischer, H. Kosina, E. Leitner, C. Pichler, H. Pimingstorfer, H. Puchner, G. Rieger, G. Schrom, T. Simlinger, M. Stiftinger, H. Stippel, E. Strasser, W. Tuppa, K. Wimmer, S. Selberherr: "The Viennese Integrated System for Technology CAD Applications"; Talk: Workshop on Technology CAD Systems, Wien; (invited) 1993-09-06 in "Proceedings Technology CAD Systems Workshop", (1993), ISBN: 3-211-82505-3, 197 - 236 doi:10.1007/978-3-7091-9315-0_10. BibTeX |
| 1. | A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, S. Selberherr: "Simulation of Void Formation in Interconnect Lines"; Talk: SPIE VLSI Circuits and Systems, Maspalomas, Spain; 2003-05-19 - 2003-05-21; . BibTeX |
| 1. | H. Puchner: "Process Integration for Deep-Submicron CMOS Technology"; TU Wien, Fakultät für Elektrotechnik und Informationstechnik, (2001), . BibTeX |
| 1. | H. Puchner: "Advanced Process Modeling for VLSI Technology"; Reviewer: S. Selberherr, W. Fallmann; Institut für Mikroelektronik, 1996, oral examination: 1996-05-31. BibTeX |
| 2. | R. Martins, H. Puchner, S. Selberherr, T. Simlinger, W. Tuppa: "VISTA Status Report June 1996"; (1996), 30 page(s) . BibTeX |
| 1. | R. Mlekus, C. Pichler, H. Puchner, S. Selberherr, W. Tuppa: "VISTA Status Report June 1995"; (1995), 17 page(s) . BibTeX |