5.1 Tunneling in MOS Transistors

The gate leakage current in contemporary MOS transistors poses a major problem for further device scaling. This section describes simulation results of MOS transistors, outlines the effect of various device parameters, shows how to account for hot-carrier tunneling in turned-on devices, and elaborates on the use of alternative dielectric materials to replace SiO$_2$ as a gate dielectric. First, however, the tunneling paths in MOS transistor structures will be reviewed.

Subsections

• 5.1.1 Tunneling Paths in MOS Transistors
• 5.1.2 Channel Tunneling
  • 5.1.2.1 Effect of the Polysilicon Gate Doping on the Channel Tunneling
  • 5.1.2.2 Effect of the Substrate Doping on the Channel Tunneling
  • 5.1.2.3 Effect of the Dielectric Thickness on the Channel Tunneling
  • 5.1.2.4 Effect of the Barrier Height on the Channel Tunneling
  • 5.1.2.5 Effect of the Carrier Mass on the Channel Tunneling
  • 5.1.2.6 Effect of the Dielectric Permittivity on the Channel Tunneling
  • 5.1.2.7 Effect of the Lattice Temperature on the Channel Tunneling
  • 5.1.2.8 Comparison to Measurements
  • 5.1.2.9 Validity of Compact Models
  
  
• 5.1.3 Source and Drain Extension Tunneling
  • 5.1.3.1 Effect of the Polysilicon Gate Doping on the Source and Drain Extension Tunneling
  • 5.1.3.2 Effect of the Substrate Doping on the Source and Drain Extension Tunneling
  • 5.1.3.3 Effect of the Dielectric Permittivity on the Source and Drain Extension Tunneling
  • 5.1.3.4 Effect of the Lattice Temperature on the Source and Drain Extension Tunneling
  
  
• 5.1.4 Hot-Carrier Tunneling in MOS Transistors
• 5.1.5 Alternative Dielectrics for MOS Transistors
• 5.1.6 Trap-Assisted Tunneling in ZrO$_2$ Dielectrics

A. Gehring: Simulation of Tunneling in Semiconductor Devices