5.1.3.4 Effect of the Lattice Temperature on the Source and Drain Extension Tunneling

Fig. 5.15 shows the effect of the temperature on the extension region gate current density. Especially the minority carriers (holes in the nMOS, electrons in the pMOS) show strongly increased tunneling current with higher temperature. Unlike in the channel tunneling case, the majority tunneling component is hardly influenced by the temperature.

Figure 5.15: Effect of the lattice temperature on the electron tunneling current (left) and the hole tunneling current (right) in the source and drain extension region of an nMOS (top) and a pMOS (bottom) with 2 nm dielectric thickness and 5e18 cm-3 substrate doping.

A. Gehring: Simulation of Tunneling in Semiconductor Devices