The physical representation specifies how a particular part of the integrated circuit will be constructed. At the lowest level it is the photo-mask data necessary to perform the several processing steps. To simplify, a model based on material layers is used. These layers (forming the layout) are afterwards translated into photo-masks. The POLY1 layer, for example, specifies where the first layer of polysilicon will be deposited to form the gate of a transistor or a local interconnection. Sometimes these layers do not relate to a specific material but to material modifications as in implantation/diffusion steps.
The layout design rules are the link between the circuit designer and the technology constraints which the former must fulfill so that the fabricated integrated circuits may achieve a sufficiently high yield. ECAD tools always provide a Design Rule Checker (DRC) to inform the designer whether they are being correctly considered or not. Aside those rules the circuit designer is usually not concerned with technology related aspects, as in the ECAD environment these are encapsulated in simple parameters like the sheet resistance of one layer, or capacitance per unit area between two layers. This makes the actual thickness of the layers of little importance. For the active devices, circuit simulator models as the SPICE Level 3 model [8] are employed. They must be calibrated for a given technology and afterwards need only relatively few layout-dependent parameters. For integrated circuits with millions of transistors, similarly to what happens in its description, a circuit-level simulation is not practical and ECAD tools provide logic-level and register level simulators as well. A very important aspect in future integrated circuit design is testability. ECAD frameworks include also tools to support the design for testability. More information in this issue and ECAD frameworks in general is given in [9][10].