A.2.3.3 Pseudo-NMOS Logic

Using a PMOS transistor simply as a pull-up device for an n-block as shown in Fig. A.13(c) is called pseudo-NMOS logic. ^A.3 Note, that this type of logic is no longer ratio-less, i.e., the transistor widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can still pull down the output safely:

$$\ensuremath{I_{\mathit{off,n}}}\xspace \ensuremath{F_{\math... ..._{\mathit{on,n}}}\xspace /\ensuremath{F_{\mathit{in}}}\xspace$$ (A.21)

The advantage of pseudo-NMOS logic are its high speed (especially, in large-fan-in NOR gates) and low transistor count. On the negative side is the static power consumption of the pull-up transistor as well as the reduced output voltage swing and gain, which makes the gate more susceptible to noise. At a second glance, when pseudo-NMOS logic is combined with static CMOS in time critical signal paths only, the overall speed improvement can be substantial at the cost of only a slight increase of static-power consumption. Furthermore, when the gate of the pull-up transistor is connected to a appropriate control signal it can be turned off, i.e., pseudo-NMOS supports a power-down mode at no extra cost.

Footnotes

... logic.^A.3

The name ``pseudo-NMOS'' originates from the circumstance that in the older NMOS technologies a depletion mode NMOS transistor with its gate connected to source was used as a pull-up device.