Bibliography

1

ALVAREZ, A.R., Ed.
BiCMOS Technology and Applications, second ed.
Kluwer, 1993.

2

ARORA, N.
MOSFET Models for VLSI Circuit Simulation.
Springer, 1993.

3

ASSOCIATION, SEMICONDUCTOR INDUSTRY.
The National Technology Roadmap for Semiconductors, 1994.

4

ASSOCIATION, SEMICONDUCTOR INDUSTRY.
The National Technology Roadmap for Semiconductors, 1997.

5

BAKOGLU, H.B.
Circuits, Interconnections and Packaging for VLSI.
Addison-Wesley, 1990.

6

BAUER, ROBERT, AND SELBERHERR, SIEGFRIED.
Capacitance Calculation of VLSI Multilevel Wiring Structures.
In Proc: Int. Workshop on VLSI Process and Device Modeling (Nara, Japan, 1993), pp. 142-143.

7

BOHR, M.T.
Interconnect Scaling - The Real Limiter to High Performance ULSI.
In Proc: Int.Electron Devices Meeting (1995), pp. 241-244.

8

BOHR, M.T., AND EL-MANSY, Y.A.
Technology for Advanced High-Performance Microprocessors.
IEEE Trans.Electron Devices 45, 3 (1998), 620-625.

9

BURR, J.B.
Stanford Ultra Low Power CMOS.
In Proc: Symposium Record, Hot Chips V (1993), pp. 7.4.1-7.4.E.

10

CAMPBELL, S.A.
The Science and Engineering of Microelectronic Fabrication.
Oxford University Press, 1996.

11

ÇILINGIROSGLU, U.
Systematic Analysis of Bipolar and MOS Transistors.
Artech House, Boston, 1993.

12

CHANDRAKASAN, A.P., AND BRODERSEN, R.W.
Low Power Digital CMOS Design.
Kluwer Academic Publishers, 1995.

13

CHANDRAKASAN, A.P., AND BRODERSEN, R.W.
Minimizing Power Consumption in Digital Cmos Circuits.
Proc.IEEE 83, 4 (1995), 498-523.

14

CHAWLA, B.R., GUMMEL, H.K., AND KOZAK, P.
MOTIS - An MOS Timing Simulator.
IEEE Trans.Circuits and Systems CAS-22, 12 (1975), 901-9C.

15

CHENG, Y., CHAN, M., HUI, K., JENG, M., LIU, ZH., HUANG, J., CHEN, K., CHEN, J., TU, R., KO, P.K., AND HU, CH.
BSIM3v3 Manual.
University of California, Berkeley, 1996.

16

CHENG, Y., JENG, M.-C., LIU, Z., HUANG, J., CHAN, M., CHEN, K., KO, P.K., AND HU, C.
A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation.
IEEE Trans.Electron Devices 44, 2 (1997), 277-287.

17

CHIK, R.Y.V., AND SALAMA, C.A.T.
Design of a 1.5 V Full-Swing Bootstrapped BiCMOS Logic Circuit.
IEEE J.Solid-State Circuits 30, 9 (1995), 972-97A.

18

CHUA, L.O., AND LIN, P.M.
Computer-Aided Analysis of Electronic Circuits: Algorithms & Computational Techniques.
Prentice-Hall, Englewood Cliffs, 1975.

19

COUGHRAN, W.M., GROSSE, E., AND ROSE, D.J.
CAzM: A Circuit Analyzer with Macromodeling.
IEEE Trans.Electron Devices ED-30, 9 (1983), 1207-1213.

20

DAVIS, J.A., DE, V.K., AND MEINDL, J.D.
A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation.
IEEE Trans.Electron Devices 45, 3 (1998), 580-58B.

21

DAVIS, J.A., DE, V.K., AND MEINDL, J.D.
A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation.
IEEE Trans.Electron Devices 45, 3 (1998), 590-597.

22

DE, V.K., EBLE, J.C., WILLS, D.S., DAVIS, J., AND MEINDL, J.D.
A Generic System Simulator (GENESYS) for Microelectronics Technology and Applications.
In Proc: GOMAC'96 Digest of Papers (1996), pp. 439-442.

23

DIAZ, C.H., KANG, S.M.(STEVE), AND DUVVURY, C.
Modeling of Electrical Overstress in Integrated Circuits.
Kluwer, 1995.

24

EL-KAREH, B.
Fundamentals of Semiconductor Processing Technologies.
Kluwer, Boston, 1995.

25

FAN, S.P., HSEUH, M.Y., NEWTON, A.R., AND PEDERSON, D.O.
MOTIS-C: A New Circuit Simulator for MOS LSI Circuits.
In Proc: Proc.Int.Symp.Circuits and Systems (1977), IEEE, pp. 700-703.

26

FERRY, D.K., AKERS, L.A., AND GREENEICH, E.W.
Ultra Large Scale Integrated Microelectronics.
Prentice-Hall, 198A.

27

FISCHER, C., HABASS, P., HEINREICHSBERGER, O., KOSINA, H., LINDORFER, PH., PICHLER, P., PÖTZL, H., SALA, C., SCHÜTZ, A., SELBERHERR, S., STIFTINGER, M., AND THURNER, M.
MINIMOS 6 User's Guide.
Institut für Mikroelektronik, Technische Universität Wien, Austria, Mar. 1994.

28

FRANCA, J.E., AND TSIVIDIS, Y., Eds.
Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, 2nd ed.
Prentice-Hall Inc., 1994.

29

FREDKIN, E., AND TOFFOLI, T.
Conservative Logic.
J.Appl.Phys. 21, 3/4 (1981), 219-253.

30

GRAHAM, M.G., AND PAULOS, J.J.
Interpolation of MOSFET Table Data In Width, Length, and Temperature.
IEEE Trans.Computer-Aided Design 12, 12 (1993), 1880-1884.

31

GRAHAM, M.G., PAULOS, J.J., AND NYCHKA, D.W.
Template-Based MOSFET Device Model.
IEEE Trans.Computer-Aided Design 14, 8 (1995), 924-933.

32

HALAMA, S., PICHLER, CH., RIEGER, G., SCHROM, G., SIMLINGER, T., AND SELBERHERR, S.
VISTA--User Interface, Task Level, and Tool Integration.
IEEE Trans.Computer-Aided Design 14, 10 (1995), 1208-1222.

33

HIRAKI, M., YANO, K., MINAMI, M., SATO, K., MATSUZAKI, N., WATANABE, A., NISHIDA, T., SASAKI, K., AND SEKI, K.
A 1.5-V Full-Swing BiCMOS Logic Circuit.
IEEE J.Solid-State Circuits 27, 11 (1992), 1568-1574.

34

JOARDAR, K., GULLAPALLI, K.K., MCANDREW, C.C., BURNHAM, M.E., AND WILD, A.
An Improved MOSFET Model for Circuit Simulation.
IEEE Trans.Electron Devices 45, 1 (1998), 134-14A.

35

KEE, T.-C., AND CONG, J.
The New Line in IC Design.
IEEE Spectrum (Mar. 1997), 52-5A.

36

KOSKO, B.
Neural Networks and Fuzzy Systems.
Prentice-Hall, 1992.

37

LARSON, L.E.
Integrated Circuit Technology Options for RFIC's - Present Status and Future Directions.
IEEE J.Solid-State Circuits 33, 3 (1998), 387-39B.

38

LIM, J.S., AND OPPENHEIM, A.V.
Advanced Topics in Signal Processing.
Prentice Hall, 198A.

39

LIU, C.T., MA, Y., LUFTMAN, H., AND HILLENIUS, S.J.
Preventing Boron Penetration Through 25-ÅGate Oxides with Nitrogen Implant in the Si Substrates.
IEEE Electron Device Lett. 18, 5 (1997), 212-214.

40

LIU, D., AND SVENSSON, CH.
Trading Speed for Low Power by Choice of Supply and Threshold Voltages.
IEEE J.Solid-State Circuits 28, 1 (1993), 10-17.

41

LIU, D.
Low Power Digital CMOS Design.
Dissertation, Linköping University, 1994.

42

MACHADO, G.A.S., Ed.
Low-Power HF Microelectronics A Unified Approach.
IEE London, 1996.

43

MASSOBRIO, G., AND ANTOGNETTI, P.
Semiconductor Device Modeling with Spice, second ed.
McGraw-Hill, 1993.

44

MEINDL, J.D.
Gigascale Integration (GSI).
In Proc: 3rd Int. Workshop on Measurement and Characterization of Ultra-Shallow Doping Profiles in Semiconductors (Mar. 1995), J. Ehrstein, R. Mathur, and G. McGuire, Eds., pp. 1.1-1.7.

45

MEINDL, J.D.
Low Power Microelectronics: Retrospect and Prospect.
Proc.IEEE 83, 4 (1995), 619-635.

46

MEINDL, J.D.
Gigascale Integration: Is the Sky the Limit?
IEEE Circuits & Devices (Nov. 1996), 19-32.

47

META-SOFTWARE, INC.
HSPICE User's Manual, 1996.

48

MOMOSE, H.S., ONO, M., YOSHITOMI, T., OHGURO, T., NAKAMURA, S., SAITO, M., AND IWAI, H.
Tunneling Gate Oxide Approach to Ultra-High Current Drive in Small-Geometry MOSFETs.
In Proc: Int.Electron Devices Meeting (1994), pp. 593-596.

49

MORIMOTO, T., MOMOSE, H.S., OZAWA, Y., YAMABE, K., AND IWAI, H.
Effects of Boron Penetration and Resultant Limitations to Ultra Thin Pure-Oxide and Nitrided-Oxide Gate-Films.
In Proc: Int.Electron Devices Meeting (1990), pp. 429-432.

50

NAGEL, L.W.
SPICE2: A Computer Program to Simulate Semiconductor Circuits.
Tech. Rep. UCB/ERL M520, University of California, Berkeley, 1975.

51

NAJM, F.N.
Estimating Power Dissipation in VLSI Circuits.
IEEE Circuits & Devices (July 1994), 11-1B.

52

PARKER, C.G., LUCOVSKY, G., AND HAUSER, J.R.
Ultrathin Oxide-Nitride Gate Dielectric MOSFETs.
IEEE Trans.Electron Devices 19, 4 (1998), 106-10A.

53

PHILIPS SEMICONDUCTORS.
Pager Applications Handbook, 1995.

54

PICHLER, CH., AND SELBERHERR, S.
Process Flow Representation within the VISTA Framework.
In Proc: Simulation of Semiconductor Devices and Processes (Wien, 1993), S. Selberherr, H. Stippel, and E. Strasser, Eds., vol. 5, Springer, pp. 25-2A.

55

PICHLER, CH., AND SELBERHERR, S.
Rapid Semiconductor Process Design within the VISTA Framework: Integration of Simulation Tools.
In Proc: Proceedings of the IASTED International Conference (Pittsburgh, PA, USA, 1993), M. Hamza, Ed., Modelling and Simulation, The International Association of Science and Technology for Development, pp. 147-150.

56

POWERS, R.A.
Batteries for Low Power Electronics.
Proc.IEEE 83, 4 (1995), 687-693.

57

PRINCE, B.
Semiconductor Memories.
Wiley, 1991.

58

RABAEY, J.M., AND PEDRAM, M., Eds.
Low Power Design Methodologies.
Kluwer Academic Publishers, 1996.

59

RIEZENMAN, M.J.
The Search for Better Batteries.
IEEE Spectrum (May 1995), 51-56.

60

SABELKA, RAINER, KOYAMA, KAZUHIDE, AND SELBERHERR, SIEGFRIED.
STAP--A Finite Element Simulator for Three-Dimensional Thermal Analysis of Interconnect Structures.
In Proc: Simulation in Industry--9th European Simulation Symposium (Passau, Germany, Oct. 1997), pp. 621-625.

61

SCHROM, G., LIU, D., PICHLER, CH., SVENSSON, CH., AND SELBERHERR, S.
Analysis of Ultra-Low-Power CMOS with Process and Device Simulation.
In Proc: 24th European Solid State Device Research Conference - ESSDERC'94 (Gif-sur-Yvette Cedex, France, 1994), C. Hill and P. Ashburn, Eds., Editions Frontieres, pp. 679-682.

62

SCHROM, G., LIU, D., FISCHER, C., PICHLER, CH., SVENSSON, CH., AND SELBERHERR, S.
VLSI Performance Analysis Method for Low-Voltage Circuit Operation.
In Proc: Fourth Int. Conf. on Solid-State and Integrated-Circuit Technology (Beijing, China, 1995), G. Baldwin, Z. Li, C. Tsai, and J. Zhang, Eds., pp. 328-330.

63

SCHROM, G., PICHLER, CH., SIMLINGER, T., AND SELBERHERR, S.
On the Lower Bounds of CMOS Supply Voltage.
Solid-State Electron. 39, 4 (1996), 425-430.

64

SCHROM, G., STACH, A., AND SELBERHERR, S.
A Consistent Dynamic MOSFET Model for Low-Voltage Applications.
In Proc: International Conference on Simulation of Semiconductor Processes and Devices (Tokyo, Japan, 1996), Business Center for Academic Societies Japan, pp. 177-17A.

65

SCHROM, G., DE, V., AND SELBERHERR, S.
VLSI Performance Metric Based on Minimum TCAD Simulations.
In Proc: International Conference on Simulation of Semiconductor Processes and Devices (Cambridge, Massachusetts, 1997), pp. 25-2A.

66

SCHUMICKI, G., AND SEEGEBRECHT, P.
Prozeßtechnologie.
Springer, 1991.

67

SCHWARZ, A.F.
Digital-Circuit Aspects and State of the Art, vol. II of Computer-Aided Design of Microelectronic Circuits and Systems.
Academic Press, 1987.

68

SCHWARZ, A.F.
General Introduction and Analog Circuit Aspects, vol. I of Computer-Aided Design of Microelectronic Circuits and Systems.
Academic Press, 1987.

69

SELBERHERR, S., AND KOSINA, H.
Simulation of Nanometer MOS-Devices with MINIMOS.
In Proc: 1990 VLSI Process/Device Modeling Workshop (Kawasaki, Japan, 1990), pp. 2-5.

70

SHIMA, T., SUGAWARA, TS., MORIYAMA, S., AND YAMADA, H.
Three-Dimensional Table Look-Up MOSFET Model for Precise Circuit Simulation.
IEEE J.Solid-State Circuits CS-17, 3 (1982), 449-454.

71

SHIMA, T., YAMADA, H., AND DANG, R.L.M.
Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation.
IEEE Trans.Computer-Aided Design CAD-2, 2 (1983), 121-126.

72

SIMLINGER, T., KOSINA, H., ROTTINGER, M., AND SELBERHERR, S.
MINIMOS-NT: A Generic Simulator for Complex Semiconductor Devices.
In Proc: 25th European Solid State Device Research Conference (Gif-sur-Yvette Cedex, France, 1995), H. de Graaff and H. van Kranenburg, Eds., Editions Frontieres, pp. 83-86.

73

STACH, A.
Simulation von MOSFET-Schaltungen.
Diplomarbeit, Technische Universität Wien, 1995.

74

SVENSSON, C., AND LIU, D.
A Power Estimation Tool and Prospects of Power Savings in CMOS VLSI Chips.
In Proc: Proc. 1994 Int. Workshop on Low Power Design (Napa, CA, USA, Apr. 1994), pp. 171-176.

75

SVENSSON, C.
High Speed and Low Power Techniques in CMOS and BiCMOS.
In Proc: IV Brazilian Microelectronics School (Recife, Jan. 1995), E. Santos and G. Machado, Eds., vol. I, pp. 265-287.

76

SWANSON, R.M., AND MEINDL, J.D.
Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits.
IEEE J.Solid-State Circuits SC-7, 2 (1972), 146-153.

77

SZE, S.M.
Physics of Semiconductor Devices, second ed.
Wiley, New York, 1981.

78

SZE, S.M., Ed.
VLSI Technology, second ed.
McGraw-Hill, 198A.

79

SZE, S.M.
High-Speed Semiconductor Devices.
Wiley, New York, 1990.

80

TAUR, Y., BUCHANAN, D.A., CHEN, W., FRANK, D.J., ISMAIL, K.E., LO, S., SAI-HALASZ, G.A., VISWANATHAN, R.G., WANN, H.C., WIND, S.J., AND WONG, H.
CMOS Scaling into the Nanometer Regime.
Proc.IEEE 85, 4 (1997), 486-504.

81

TSIVIDIS, Y.P.
Operation and Modeling of the MOS Transistor.
McGraw-Hill, 1987.

82

TSIVIDIS, Y.P.
MOSFET Modeling for Analog Circuit CAD: Problems and Prospects.
IEEE J.Solid-State Circuits 29 (1994), 210-216.

83

VITTOZ, E.A.
Design of Low-Voltage Low-Power IC's.
In Proc: 23rd European Solid State Device Research Conference - ESSDERC'93 (Gif-sur-Yvette Cedex, France, 1993), J. Borel, P. Gentil, J. Noblanc, A. Nouailhat, and M. Verdone, Eds., Editions Frontieres, pp. 927-934.

84

VITTOZ, E.A.
Analog VLSI Signal Processing: Why, Where and How?
Journal of VLSI Signal Processing 8 (1994), 27-44.

85

WANG, CH., AND ROY, K.
Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Approaches.
IEEE Trans.VLSI Systems 6, 1 (1998), 134-140.

86

WANG, N.
Digital MOS Integrated Circuits.
Prentice-Hall, 198B.

87

WESTE, N.H.E., AND ESHRAGHIAN, K.
Principles of CMOS VLSI Design, second ed.
Addison Wesley, 1993.

88

WOLF, S.
Silicon Processing for the VLSI Era.
Lattice Press, 1990.

89

WOLF, S.
The Submicron MOSFET, vol. 3 of Silicon Processing for the VLSI Era.
Lattice Press, Sunset Beach, California, 1995.

90

YOURDON, E., AND CONSTANTINE, L.L.
Structured Design.
Prentice-Hall, 197B.