3.2.2.1 Standby Mode

A computer or processor in standby mode does not perform any computations but is ready to resume normal operation, usually within a specified minimum amount of time. The percentage of time at which the computer is in standby mode is the standby ratio . The goal of optimum power efficiency at a given performance remains the same, but the term ``power'' now refers to the total average power consumption which is the weighted sum of active-mode power consumption and standby-mode power consumption:

$$\ensuremath{P_{\mathit{tot}}}\xspace = (1-\ensuremath{{\mat... ...th{{\mathit{sr}}}\xspace \ensuremath{P_{\mathit{stb}}}\xspace$$ (3.17)

The simplest form of standby mode is to operate the processor in the normal active state but with a lower or zero clock frequency in an idle mode. In this case the switching energy can be expressed as

$$\ensuremath{E_{\mathit{s}}}\xspace = \ensuremath{C_{\mathit... ...f}}}\xspace }{\ensuremath{I_{\mathit{on}}}\xspace }} \right] ,$$ (3.18)

i.e., the effective activity ratio becomes $\ensuremath{{\mathit{ar}}}\xspace (1-\ensuremath{{\mathit{sr}}}\xspace ) < \ensuremath{{\mathit{ar}}}\xspace$. Thus, the optimum value for can be much smaller than that obtained from minimizing the active power only. The situation for dynamic logic is similar as the lower clock frequency in standby operation requires higher leakage time and thus a lower . Note that in order to maintain the required performance at lower off-state current the supply voltage must be increased, which increases the active power consumption.

The essential problem associated with this simple standby operation is that the required low for a high standby ratio, which is quite common in portable applications such as notebooks or palmtops, leads to a tradeoff between active and standby mode, which may effectively prevent an Ultra-Low-Power technology. Potential ways to tackle tackle this problem are:

1.

Turn off the power supply of unused parts of the chip (power-down mode).

This approach may be too expensive because of the chip area consumed by the power switches. However, when the switches are already present as part of a power-supply circuit the only additional circuitry needed for the power-down mode is a suitable control of the power supply (cf. Section 2.8).

Furthermore, certain logic styles provide an implicit infrastructure for power-down modes. One example is pseudo-NMOS logic (see Section A.2.3.3) which allows to turn off individual logic blocks with the gate of the PMOS pull-up transistor

2.

Use multiple threshold voltages in combination with power-down modes.

Internal states of the high-speed core of a chip are transferred to a memory which uses high- transistors before the core is turned off.

3.

Use medium threshold voltage and variable supply voltage.

In standby mode is decreased to a minimum of $\ensuremath{V_{\mathit{DD,min}}}\xspace \approx 200mV$ to reduce the standby power by a factor of $\ensuremath{V_{\mathit{DD}}}\xspace /\ensuremath{V_{\mathit{DD,min}}}\xspace$. As the for normal operation is larger there is still a tradeoff between active and standby power.

4.

Well-biasing

A reverse bias on the wells is used to increase the the threshold voltage so as to turn the devices off (cf. Section 2.7.2). This approach, however, has some disadvantages, especially, it cannot be implemented effectively for fast deep-sub-micron devices.