4.4.3.1 MPS Diode Structure

A cross-section of a 4H-SiC MPS rectifier is shown in Fig. 4.12. An MPS diode consists of inter-digitated Schottky and p+ implanted areas. For on-state voltage drops less than 3V, only the Schottky regions of the diode conduct and thus the device is also referred to as a Junction Barrier Schottky (JBS) diode.

Figure 4.12: Cross section of a merged pin Schottky diode in SiC.

The on-state voltage drop of the MPS diode is determined by the resistance of the drift region, the metal-SiC barrier height, and the relative area of the Schottky vs. the p+ implanted regions. For reverse bias conditions, the depletion regions from adjacent p+ implanted regions pinch-off the leakage current arising from the Schottky contacts of the device. The leakage current in the Schottky regions occurs due to the Schottky barrier lowering at the metal-n- junction. The presence of the adjacent p+ implanted regions reduces the electric field at the metal-SiC junction because of two-dimensional charge sharing. This property is especially useful when the diode is operating at elevated temperatures since the effect of Schottky barrier lowering is enhanced with increasing temperature.

The detailed design of the 1500-V MPS diodes are described in [178]. The design primarily consists of selecting the optimum Schottky metal, size and spacing of the p+ implanted regions, and thickness and dopant density of the drift region. It is important to achieve a good quality Schottky interface to obtain a low on-state drop when operated in the JBS diode mode. The metal-SiC barrier height of the Schottky metal should be low enough to give a low on-state voltage, while still enabling effective pinch-off during the off state. This is achieved using Ni as the Schottky metal.

The diode has an epitaxial layer thickness of 8.5 $\mu$m over 4H-SiC n+ substrate doped at 9$\times$10$^{15}$ cm$^{-3}$ to obtain the desired blocking voltage capability of 1500 V. The relative area and geometrical layout of the p+ implanted region are fundamental design parameters that affect the device characteristics. A large p+ implanted area is expected to result in a higher on-state voltage due to a smaller Schottky conducting area, but may offer lower leakage due to a more effective pinch-off of the Schottky portion. The optimized diodes produced in [178] have a 2 $\mu$m wide p+ implanted region with 4 $\mu$m spacing.

Table 4.3: Summary of optimized device parameters used for a simulation of MPS diode.

parameter	value
p+ length, thickness, and concentration	$2\,\mathrm{\mu}$m, $1.5\,\mathrm{\mu}$m, $1.0\times 10^{17}$ cm$^{-3}$
n- epilayer thickness and concentration	$8.5\,\mathrm{\mu}$m, 9 $\times10^{15}$ cm $^{-3}$
spacing between p+ implanted regions	$4.0\,\mathrm{\mu}$m

T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation