CGG  (CERVS GRID GENERATOR) was developed at the Institute for Microelectronics. It supports the generation of two-dimensional and three-dimensional high quality Delaunay meshes. It is a special purpose grid generator that is optimized for the generation of simulation grids for device simulators. Compared to other gridding algorithms CGG takes into account the very small channel regions under, e.g., the gate of a MOSFET transistor. This special treatment is achieved by inserting points along an expected channel region. To insert the points at the right position CGG solves the Laplace equation in the semiconductor region. Points are then inserted along the resulting iso-potential lines. This ensures that the points (and the resulting grid lines) are arranged parallel to the estimated current flow through the channel. This in turn keeps the discretization error of the current flow equation at a minimum. For the actual Delaunay gridding process the grid generators TRIANGLE (two-dimensional) and DELINK (three-dimensional) are used.
In order to implement the Gridder interface described above CGG needs extra information like the name of the contact regions where the voltages are applied and the lateral and vertical point densities. Since this data is only useful to this specific grid generator there is no according method in the general Gridder interface. Instead, this information is passed directly to the constructor of the CGG class. Alternatively, CGG can be instructed to read an input deck containing all specific settings.