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4.4 Device Optimization by Three-Dimensional
Diffusion Simulation

A major goal in the process development of high voltage processes is the design of devices with given breakdown voltages and low on-resistances. To reach this goal it is necessary to optimize the space charge regions of the device. Unfortunately these effects are three-dimensional and a device optimization needs the support of accurate three-dimensional process and device simulation.

The requirement for a low on-resistance ( $ \mathrm{R_{on}}$) is to design a single device as small as possible. The reduction of space charge regions is limited by the dopant surface concentration of the wells which may result in impact ionization effects in case of too high doping concentrations. On the other hand, lowering the doping concentrations is limited by the required punch-through voltage. To fulfill these conflicting criterions the doping concentrations must be optimized.

4.4.1 Simulated Structure

The investigated device is the tip of a drain finger of a high voltage PMOS transistor. For proper insulation of a p-type MOS transistor in a p-doped substrate, the whole transistor structure must be placed in a n-doped well located inside the substrate (NWell). The resulting pn-junction blocks the two different regions. Under the drain and source regions of the transistor, higher doping concentrations for electrical strength are required, whereas under the gate and near the surface lower doping concentrations are required to prevent impact ionization. These effects are combined in a deep NWell under the active drain and source regions and a shallow NWell in peripheral regions of the drain and source contact, called SDNTUB. The main drain and source regions of the transistor have to be constructed by a p-doped region under the contacts, located close to the surface of the wafer. This region is realized by a p-doped tub (PTUB). In combination with the SDNTUB a second pn-junction is built. Overall, a pnp-structure is formed by the PTUB, SDNTUB, and the substrate and under normal operation the PTUB/SDNTUB junction is biased in reverse direction.

To optimize the main characteristic of the PMOS transistor it is necessary to ensure that no three-dimensional effects dominate the device behavior. The optimal drain finger layout ensures that applying maximal $ \mathrm{V_{dd}}$ causes no punch-through between PTUB and substrate and no avalanche breakdown occurs at the surface of the wells.

The anticipated netto doping distribution of the three-dimensional structure can be seen in Figure 4.1. For better understandability of the nomenclature of the layers, the pn-junctions and the names of the layers are plotted.

The complete device is embedded in the SNTUB so that there is no direct connection between PTUB and substrate. Only in the area of the PTUB, the DNTUB determines the distance between the pn- and the np-junctions. The PTUB/DNTUB mask layout is given in Figure 4.2, which shows that the DNTUB mask is enclosed by the PTUB mask. To enlarge the distance between the two junctions it is necessary to use a long DNTUB diffusion time so that the DNTUB dopants nearly diffuse spherically at the tip of the drain finger. This long DNTUB diffusion finally leads to a DNTUB formation which starts outside of the PTUB mask. The three-dimensional consideration is necessary because the spherical diffusion of the DNTUB dilutes the DNTUB concentration in the area of the finger tip and thus reduces the punch-through voltage of the PMOS device.

Figure 4.1: Netto doping of the semiconductor segment.

Figure 4.2: Well mask layout of the high voltage device.
Mask layout of the drain region of the transistor
Mask layout of the finger tip

\includegraphics{ex5/greenline} mask for boron implantation
\includegraphics{ex5/yellowline} mask for phosphorus implantation

4.4.2 Comparison of Simulation Approaches

The conventional procedure is to simulate the whole ion implantation process first [24] and then the three-dimensional transient diffusion [48]. Thereby both steps require a particularly fine grid to achieve appropriate accuracy [15] and, therefore, the vast amount of memory and huge calculation times constitute prohibitive demands in practice.

Because of the long diffusion ranges, the exact simulation of the ion implantation process can be neglected and the implanted ions were assumed only located at the top of the wafer. With this simplification the final diffusion profile inside the wafer can be calculated by the Green's Function method. A grid is only necessary at the surface of the wafer and the resulting doping distribution can be calculated at any point of interest.

4.4.3 Calibration and Evaluation

The diffusion model has to be calibrated by the two-dimensional simulation results which are available far away from the tip of the finger. The simulated drain current versus the drain-substrate-voltage of the two-dimensional cut is shown in Figure 4.3.

The assessment criterion of the new layout parameters is the fact that the dopant concentration of the PTUB/SDNTUB junction at the surface of the wells is the same for the two-dimensional case and the three-dimensional finger case. This ensures that the breakdown at the surface in the three-dimensional structure takes place in the same voltage range as compared with the two-dimensional structure.

Figure 4.3: Two-dimensional simulation of the drain-current far away from the tip of the finger.

4.4.4 Results

The simulation results show that the spherical out-diffusion of the DNTUB is larger than expected due to the large NTUB depth. This depth is about 7.5 micron in the two-dimensional simulation. The spherical diffusion length is also of the same size from the top of the DNTUB finger to the direction of the two-dimensional case. In fact, the two-dimensional situation is given when the DNTUB mask is enlarged by about 7 micron as compared to Figure 4.2. This means that the DNTUB mask can even exceed the PTUB mask. However an enlargement of 7 microns would cause impact ionization near the top of the PTUB surface. So the limiting case of the DNTUB enlargement is the dopant concentration of the two-dimensional simulation at the surface of the junction. This critical concentration is given when the DNTUB mask is shifted by 2 microns towards the PTUB mask. The different surfaces of the pn-junctions are shown in Figure 4.4(a) for the original mask setting and Figure 4.4(b) for the improved finger design.

Another interesting effect is that the punch-through in the three-dimensional case does not occur directly under the symmetry line of the finger (see Figure 4.5(a)). The explanation is that the DNTUB dopants diffuse spherically while the PTUB dopants diffuse cylindrically. Therefore, the punch current has its maximum density near the edge of the PTUB mask. For comparison the space charge region of the enlarged finger is shown in Figure 4.5(b).

The simulation results are validated by a set of test devices. Figure 4.6 shows the punch current dependency of the finger elongation starting with the initial layout shown in Figure 4.2.

With these careful considerations the device has been optimized to fulfill the electrical requirements, particularly with respect to punch-through between the junctions and breakdown by impact ionization. Without the outlined simulation methodology it would not have been possible to fully optimize the structure.

Figure 4.4: Relevant iso-surfaces of the phosphorus doping and the pn-junctions of the finger. The relevant boron surface is approximatively represented by the pn-junction which is located under the surface of the wafer.

The original finger layout.

The $ 2  \mathrm{\mu m}$ enlarged finger layout.

Image g pn-junction, where the upper one also represents a boron iso-surface
Image y phosphorus iso-surface

Figure 4.5: Surfaces surrounding the space charge regions between both pn-junctions.
The original finger layout.

The $ 2  \mathrm{\mu m}$ enlarged finger layout.

Figure 4.6: Simulation of the original finger structure compared to the measurement of four test wafers.

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Next: 5. Grid Generation for Up: 4. An Alternative Approach Previous: 4.3 Advantages of the

J. Cervenka: Three-Dimensional Mesh Generation for Device and Process Simulation