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6.2 Development of an EEPROM Memory-Cell

In the next example, the interaction of the different tools for the development of an EEPROM memory cell will be demonstrated.

The goal was to extract characteristic values of an EEPROM memory cell. For timing analysis, the capacitances between the semiconductor segment and the control- and floating-gate are crucial. To allow the extraction of these capacitances the three-dimensional extraction of the electric field is necessary. As it is impossible to describe such a complex device structure manually, the device structure had to be generated by a fully three-dimensional simulation of all the manufacturing processes of the device. The cross section of the memory cell and its typical layer thicknesses are shown in Figure 6.8.

Figure 6.8: The cross section and typical layer thicknesses of the memory cell.

$\textstyle \parbox{8cm}{\includegraphics[width=\linewidth]{picsconveps/zelle2}}$         \fbox{\begin{tabular}{lr}
Tunnel Oxide & 8.5  nm\\
ONO & 24  nm\\
Floating Gate & 200  nm\\
Control Gate & 250  nm\\

6.2.1 Process Simulation of the Memory-Cell

Figure 6.9: Expanded two-dimensional structure -- 8,800 points, 51,000 tetrahedrons.

                \includegraphics[width=10.5cm]{picsconveps/structure} \includegraphics[width=2.5cm]{picsconveps/materialee}

Figure 6.10: Floating-gate and first oxide layer -- 18,300 points, 69,000 tetrahedrons.

                \includegraphics[width=10.5cm]{picsconveps/ono1} \includegraphics[width=2.5cm]{picsconveps/materialee}

Figure 6.11: ONO layers added -- 70,300 points, 341,000 tetrahedrons.

                \includegraphics[width=10.5cm]{picsconveps/ono31} \includegraphics[width=2.5cm]{picsconveps/materialee}

Figure 6.12: Final structure of the EEPROM cell -- 76,700 points, 402,000 tetrahedrons.

                \includegraphics[width=10.5cm]{picsconveps/poly21} \includegraphics[width=2.5cm]{picsconveps/materialee}

While initial process steps like the oxidation of the silicon wafer for generating the field-oxide can be performed by a two-dimensional analysis, the following process steps have to be performed fully three-dimensional:

6.2.2 Electrical Analysis of the Device

The final electrical simulation and capacitance extraction is performed with the simulator STAP, part of the Smart Analysis Programs [55][56]. This is a three-dimensional interconnect simulator, which computes the field distribution inside the simulation area using Finite Elements. The capacitances are calculated via the energy of the electric field [54]. The result of the field calculation can be seen in Figure 6.13. An explanation for the large number of grid points and tetrahedrons is a global grid refinement of the program STAP, where each tetrahedron is split into 8 smaller ones. The floating-gate and the control-gate segments are connected to constant potential, 0  V and 1  V, respectively. The influence of the silicon segment is taken into account as a ground plane (connected to 0  V). Within this figure, the contact regions, which are the floating-gate, the control-gate, and the silicon segment, have been removed. Results of the capacitance extraction are shown in Table 6.2.

Figure 6.13: Distribution of the electric potential, 0 V at the floating-gate, 1 V at the control-gate -- 640,000 points, 3,400,000 tetrahedrons.

\includegraphics[width=10cm]{ex3pics/pot.eps}         \includegraphics[width=2cm]{ex3pics/bar.eps}

It is remarkable that the basically simple silicon/oxide-structure, starting with 51,000 tetrahedrons, increases to 400,000 tetrahedrons and the memory limits during process simulation are reached. However, the field extraction is performed by 3,400,000 tetrahedrons and the memory consumption is not of this magnitude. The enormous process simulation overhead in memory consumption is caused by the required functionality of the process simulation tools. In detail, for deposition and etching at least two grids, the original and the modified grid, are stored during each simulation step. Additional functionality, such as neighborhood information, surface information, an octree for point location and additional attributes have to be stored in the data structures. For performing the interconnect simulation, only the final grid and potential attributes are necessary. For future simulations of more complex three-dimensional structures further work on data reduction and surface smoothing will be necessary.

Table 6.2: Results of the capacitance simulation.
$ \mathrm{C_{Si-Cg}}$ Capacity silicon - control-gate $ 0.82 \times 10^{-16}$  F
$ \mathrm{C_{Si-Fg}}$ Capacity silicon - floating-gate $ 1.1 \times 10^{-16}$  F
$ \mathrm{C_{Cg-Fg}}$ Capacity control-gate - floating-gate $ 2.3 \times 10^{-16}$  F

next up previous contents
Next: 7. Conclusion and Outlook Up: 6. Applications of the Previous: 6.1 Device Simulation of

J. Cervenka: Three-Dimensional Mesh Generation for Device and Process Simulation