2.4 Local Oxidation Nanolithography

In Section 1.1, an overview of Complementary Metal Oxide Semiconductor CMOS processing technologies is given. However, the semiconductor industry is continuing to attempt to follow Moore's law [154] using the recently coined ``More Moore'' and ``More-than-Moore'' [2] approaches. ``More Moore'' is the scientific community's attempt to continue doubling the number of transistors every $ \sim $two years, while ``More-than-Moore'' relates to solving challenges for application driven components. It is essential that these approaches work together in order to continue current scaling trends into the near and distant future [2].

In order to continue with ``More Moore'', it is evident that standard lithographic techniques are not sufficient in providing the necessary steps for the generation of modern nanosized devices. The drive to generate smaller and smaller devices leads to various attempts to replace conventional optical and electron beam lithographies with other lithographic technologies [61], [198]. The 248nm and 193nm ultraviolet lithography is approaching the limit of its potential and in order to continue with ``More Moore'' various alternatives have been examined [69]. Although 157nm lithography has been introduced in order to enable the production of sub-50nm features, the scientific community opted to mainly employ high-index immersion lithography [182] to the 193nm technology instead of dealing with numerous technical and economic issues which arise with the introduction of a new 157nm technology [24]. With high-index immersion lithography, the 193nm node was used to generate sub-40nm features [182]. Beyond this node, the global semiconductor manufacturer consortium International Sematech, suggested that EUV, or X-ray lithography [18], is likely to become the community standard [198]. More recently, EUV has been studied in order to generate sub-10nm patterns [166]. However, many issues still remain unsolved and the lithographic performance for patterns generated by IBM and AMD showed much to be desired with regard to uniformity, overlay, and defect generation [70]. AMD suggested that it is attempting to include EUV in its high-volume processing chain for the 16nm node by 2014 [70]. Although a promising technology Extreme Ultra Violet (EUV) is a very expensive and complex technique which must be performed in a vacuum. Additional sources of contention with EUV is equivalent to issues which arise with electron beam lithography; the mirror responsible for collecting the light is directly exposed to the plasma, making it vulnerable to damage from the high-energy ions [194]. Due to these combined issues for optical, electrical, and X-ray lithographies, a possible low cost route for lithography was sought out, which uses a direct localized printing technique [30].

Some nanoprinting techniques that were experimented with through the 1990's in order to advance lithography techniques for nanosized devices are magnetolithography [48], soft lithography [230], and Scanning Probe Microscopy (SPM), which include nanoimprint lithography [31], dip-pen nanolithography [174], and Local Oxidation Nanolithography (LON) [38].

Magnetolithography is based on applying a magnetic field on the substrate using magnetic masks in order to define a spatial distribution of magnetic nanoparticles. The nanoparticles react chemically with the substrate, acting as a mask for desired substrate regions. Magnetolithography is a bottom-up technique, which has the drawback of a relatively low throughput, which can be overcome with expensive and defect-prone parallelism [1], [8], [129], [212].

In soft lithography, an elastometric stamp with patterned relief structures on its surface is applied to generate structures with feature sizes ranging from 30nm to 100$ \mu $m. This lithographic method results in stamp deformations, with the stamp shrinking or swelling during the curing process, as well as substrate contamination, resulting in a reduced quality printed image [230].

Nanoimprint lithography deals with printing a template pattern on a mask using a UV photoresist or a spin coated polymer on the substrate. The simplicity of the method makes it attractive for manufacturing; however problems persist with overlay, defects, and template wear [79].

Dip-pen nanolithography is used to directly imprint chemical patterns on surfaces with nanoscale precision using an AFM [23].

Similarly, LON uses an AFM in order to deposit a new layer on a wafer surface, such as the deposition of silicon dioxide on a silicon wafer [38]. The main advantage which LON has over other attempts to generate nanosized patterns on a wafer surface is its ability to be performed at room temperature in an air ambient and across a large range of materials [198]. This section deals with the development of the LON technique and how the interactions between a STM or AFM with the silicon surface results in oxide growth.


L. Filipovic: Topography Simulation of Novel Processing Techniques