4.2 Bit Cost Scalable Memory Holes

There is a constant drive in the semiconductor industry to fit as many components as possible onto a single chip, which is consistently decreasing in size. Memory structures are also prone to such attempts at miniaturization since memory requirements and needs are constantly increasing, while chip area is decreasing. Current flash memory technologies are based on NAND or NOR gates. The NAND gate based memory cells are primarily used for memory cards, Universal Serial Bus (USB) flash drives, and solid state drives, mainly to obtain high density storage. The NOR gate based memory cells are used in mobile phones, printers, controllers and devices which require fast read access. There are signs which suggest a significant increase in the memory market in the coming years because of the extreme amounts of information which are becoming available. The amount of information produced by human activities is growing exponentially and the current storage mechanisms are unable to keep up [163]. This section will describe a novel technology for a three-dimensional stacked Bit Cost Scalable (BiCS) memory and the major concerns regarding its potential, which are due to processing complexities and limitations. A model for etching memory holes through a multi-layered silicon and silicon dioxide structure is presented.


L. Filipovic: Topography Simulation of Novel Processing Techniques