5.2 Modeling BiCS Memory Hole Etching

In order to etch BiCS memory holes, a sequence of SiO$ _2$ and Si etching is required, as is depicted in the two-dimensional cross section of the memory hole in Figure 5.5.

Figure 5.5: Two-dimensional image of the hole which needs to be etched through layers of Si and SiO$ _2$ in order to generate a BiCS structure.
It is important to note that etching deformations in one layer will lead to deformation in the layer below and so on, limiting the total number of layers through which etching is possible. This limits the cost effectiveness of the BiCS memory scheme, as is explained in Section 4.2.1. This section serves to generate etch models in the LS environment for silicon and silicon dioxide, which then must be joined in order to etch the complete memory hole.


L. Filipovic: Topography Simulation of Novel Processing Techniques