6.3.4 Silicon Nanowire Transistor

All modern transistors have a gate electrode, which controls the flow of holes and electrons between the source and drain contacts. In CMOS transistors, this modulation relies on the presence of a junction between the channel and the source and drain contacts. With the decreasing dimensions of modern transistors, generating these junctions is becoming increasingly difficult [92]. The first patented field effect transistor, suggested by Julius Edgar Lilienfeld [127], [128] in the 1920's was a junction-free device. The device was designed such that charge carriers could be depleted by the actions of the gate. However, in order to be able to fully turn off the device, a very thin nanoscale channel (nanowire) is required. The technology for generating such thin structures did not exist until recently [92]. In fact, the first junctionless transistor was manufactured in 2010 by Colinge et al. [35]. Using standard Silicon on Insulator (SOI) technology and electron-beam lithography, they were able to produce the first junctionless transistor. Since then, it has been shown that AFM nanolithography processes could also be used in order to generate the nanowire required to connect the source and drain sides of the transistor [43], [117]. This process can be performed at room temperature and with minimal damage to the crystalline structure of silicon, which is commonly introduced due to the highly energetic electrons which are an integral part of electron beam lithography [93], [117]. A type of junctionless transistor, the Silicon Nanowire Transistor (SiNWT), fabricated by Hutagalung using non-contact AFM nanolithography is described in [85]. The generated SiNWT, after AFM nanolithography and selective wet etching, is shown in Figure 6.14.

The simulation process, which follows the fabrication process from [85] is shown in Figure 6.15. The yellow (top) surface represents the silicon dioxide (SiO$ _2$) mask layer, the red (second) surface represents the top of the silicon surface, while the green (third) and dark blue (fourth) surfaces represent the top and bottom of the buried oxide (SiO$ _2$) within the SOI wafer. The light blue (bottom) surface depicts the bottom of the wafer, such that the volume between the two blue surfaces is the silicon wafer. The first step is the generation of the oxide mask layer, shown in Figure 6.15a, followed by the application of the silicon nanowire using an AFM in NCM in Figure 6.15b. Subsequently, TetraMethylAmmonium Hydroxide (TMAH) is used in order to selectively and anisotropically etch away the silicon, shown in Figure 6.15c. TMAH is a wet etching process which has an approximate 1:1000 etch ratio for SiO$ _2$ with respect to silicon. The final step is the removal of the silicon dioxide, which is done once again using wet etching, but with hydrofluoric acid (HF). This acid selectively etches silicon dioxide, leaving behind the desired nanowire pattern on the SOI wafer as shown in Figure 6.15d. The AFM lithography simulation for the nanowire assumed a pulse time of 0.25ms and a bias voltage of 16V in a 55% humidity ambient. The final nanowire has an approximate width of 100nm, such as suggested in [85].

Figure 6.14: SiNWT generated using AFM nanolithography and wet etching [85].

Figure 6.15: Topography simulation steps for the fabrication process for a silicon nanowire transistor. (a) Initial lithography to place oxide as a mask for source, drain, and gate contacts. (b) Nanowire generated using AFM to connect the source and drain contacts. (c) TMAH etching of silicon, with SiO$ _2$ serving as a mask. (d) HF etching of SiO$ _2$, leaving the desired pattern on the silicon surface.
(a) Initial lithography.
(b) Nanowire generated using AFM.
(c) TMAH etching of silicon.
(d) HF etching of SiO$ _2$.

L. Filipovic: Topography Simulation of Novel Processing Techniques