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7.2 Interconnects

An important field of application is the capacitance extraction and thermal analysis of interconnects in semiconductor devices. The finite element package SAP [140] can be used for electro-thermal interconnect simulation. It contains a layer-based preprocessor to generate three-dimensional meshes from cross-sections. This limited approach forces a uniform element size along one coordinate axis as was described in Section 4.2.1. The lateral mesh density must be identical for all cross-sections. Figure 7.10 shows the interconnects for a region of a DRAM. With some restrictions the layer-based preprocessor of SAP allows to apply a linear transformation function to a layer. The conductors depicted in Fig. 7.10 were modeled in such a way. The mesh generated with SAP for such a layered solid model is shown in Fig. 7.11. The same interconnect structure meshed with the fully unstructured modified advancing front method is presented in Fig. 7.12. The variation of the element size in Fig. 7.12 compared to the mesh in Fig. 7.11 shows the increased flexibility of the approach.

Figure 7.10: Structure of the discretized conductors in a DRAM ($0.8\mu m$ x $3.2\mu m$).
\includegraphics [width=0.6\textwidth]{ppl/inter1.eps}

Figure 7.11: Mesh generated with the layer-based method, 6480 tetrahedra. The vertical propagation of refinement through all layers can be observed.
\includegraphics [width=0.42\textwidth]{ppl/inter2.eps}

Figure 7.12: Fully unstructured Delaunay mesh of the DRAM, 5290 tetrahedra.
\includegraphics [width=0.42\textwidth]{ppl/inter33.eps}

A much bigger challenge arises if the solid model is not edited but rather derived from process simulation. The structures evolving after etching and deposition steps are more complex than can be handled with methods such as the layer-based method. The output of a topography simulator is often highly refined to match the required resolution for the manipulation of the structure. Such a more complex two layer interconnect structure typically evolving from the simulation of semiconductor processes is shown in Fig. 7.13 and Fig. 7.14. In this example the layout consists of two masks which define the metal lines for each of the two layers. A three-dimensional etch simulation with ETCH3D [170] is used to derive the structure from this layout data. Each layer results from directional etching of a metal film which is masked with the resist pattern. After stripping the resist for the first layer, an isolating oxide layer is deposited. The second layer metal film is deposited on top of this oxide layer. The structure depicted in Fig. 7.13 shows the state after stripping the resist for the second layer. The isolating oxide layer between the two metal films and before further oxidation is shown separately in Fig. 7.14.

The geometrical data available to the mesh generator consisted in this case only of the polygonal description of the material interfaces. The closed boundary representations of the material segments were generated during the meshing process. The seed triangles for the enclosed segments of each material were extracted from the interface data given by the topography simulator.

Figure 7.13: Silicon bulk (5139 elements) and four metal lines (51682 elements).
\includegraphics [width=0.8\textwidth]{ppl/}

Figure 7.14: Oxide layer, 47203 elements.
\includegraphics [width=0.8\textwidth]{ppl/}

next up previous contents
Next: 7.3 Chemical Vapor Deposition Up: 7. Examples Previous: 7.1 CAD
Peter Fleischmann