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Most of the bipolar logic families such as T^{2}L and I^{2}L are
saturatedmode logic circuits. As the transistors are driven into saturation,
circuit speed is diminished. Several techniques have been considered to
prevent saturation such as Schottky clamping. To prevent the transistors from
saturating, the current and voltage swings have to be limited. The operation
of nonsaturating logic is based on current switching and is hence known as
current mode logic (CML). A CML gate is an emitter coupled logic (ECL) gate
stripped of the emitterfollower [11] which
provided the power gain for driving external circuits. Also the gate
propagation delay is increased by the transit time of the transistor, the
overall speed is more than compensated by the reduced RC time constant that
the external load would have placed on the switching pair [71].
However, due to the improved fabrication technologies the situation is
considerably different from that in which ECL was developed and the
emitterfollower can be considered an unnecessary artifact of the past.
Figure 7.14:
Fivestage CML ring oscillator

The DC transfer characteristic of a single stage without load from
Fig. 6.12 can be approximated by assuming a simple
EbersMoll model for the transistors [71,1]. The input
voltage is compared to the reference voltage
V_{in} 
= 
 V_{ref} 
(7.8) 

= 
V_{BE1}  V_{BE2} 
(7.9) 

= 
V_{T}^{ . }ln
 ln
= V_{T}^{ . }ln
. 
(7.10) 
Neglecting the base currents and R_{E}, the sum of the collector currents
must be equal to the current flowing through the current source, hence
I_{C1} + I_{C2} = I_{t} . 
(7.11) 
With the voltage drops at R_{C} both
and
can be calculated as

= 
 I_{C1}^{ . }R_{C} =  
(7.12) 

= 
 I_{C2}^{ . }R_{C} =  
(7.13) 
with
V_{S} = I_{t}^{ . }R_{C} 
(7.14) 
The voltage gain of the single inverter is
A_{v} =
=  
(7.15) 
with a maximum at
V_{in} = 0 V
A_{v}^{max} =  
(7.16) 
For
A_{v}^{max} greater than unity V_{S} must be greater than
4^{ . }V_{T}. The larger gain is used by the system to account for static
and dynamic voltage drops that occur in practice. In practice, a minimum
gain of 4 is needed to provide sufficient noise margins [52,74].
For the simulation
V_{S} = 20^{ . }V_{T} has been assumed hence a gain of
5 could be expected. When considering an inverter chain consisting of 5
CML inverters as shown in Fig. 7.14 the total gain
occurring at the last output node is
( 5)^{5} = 3125. With such a high gain,
the circuit is too sensitive to the voltage changes occurring during iteration
so no solution can be found without a proper initialguess using conventional
techniques. However, using the shunt conductance technique with
= 4
a DC operating point can be easily obtained with only 34 iterations.
First, starting from the operating point obtained above, the DC openloop
transfer characteristic was determined which is shown in
Fig. 7.15. The voltage gain of the circuit is shown in
Fig. 7.16 which corresponds approximately to the
simple results obtained above.
As there is no unique operating point for the closedloop one of the node
voltages had to be fixed to force the circuit into an initial state from which
oscillations can start. Hence, the input voltage of the first inverter was
fixed to 0 V during the operating point calculation.
Figure 7.15:
Openloop DC transfer characteristic for the CML ring oscillator.

Oscillations start immediately with a frequency
f_{DD} = 6.8 GHz for DD and
f_{HD} = 10.6 GHz for HD which
gives a relative difference of 36% for the DD model
(Fig. 7.17). This is due to the velocity overshoot which
occurs in the basecollector space charge region which cannot be modeled using
a DD transport model. The current levels are approximately equal in both
cases as shown in Fig. 7.18.

Figure 7.16:
Openloop gain for the CML ring oscillator at the last three stages.

Figure 7.17:
Oscillation of node voltage
of the fivestage CML ring oscillator.
Large discrepancies between DD and HD are observed.

Figure 7.18:
Oscillation of the collector current of T_{1} of the fivestage CML ring oscillator.
Current levels are approximately the same for both transport models.

Next: 7.4 Thermal Analysis of
Up: 7. Simulation Results
Previous: 7.2 FiveStage CMOS Ring
Tibor Grasser
19990531