next up previous contents
Next: B. Device Model Implementation Up: Dissertation Grasser Previous: 8. Outlook


A. Thermal Equivalents

Figure A.1: a) Geometry and b) temperature distribution of a material block.
\begin{figure}
\begin{center}
\resizebox{16cm}{!}{
\psfrag{A} [c][c]{$\scriptsty...
...degraphics[width=16cm,angle=0]{figures/thermal-geo.eps}}\end{center}\end{figure}

Solving the one-dimensional static lattice heat flow equation

div SL = H - $\displaystyle \rho_{L}^{}$ . cL . $\displaystyle {\frac{\partial T_{L}}{\partial t}}$ (A1)
SL = - $\displaystyle \kappa_{L}^{}$ . grad TL (A2)

one can derive a thermal equivalent model for a device with a geometry as shown in Fig. A.1a. With the boundary conditions TL(- a) = T1 and TL(a) = T2 and under the assumption of constant heat generation H the solution for the lattice temperature inside the device reads

TL(x) = $ {\frac{P_{E}}{8 \cdot G_{\mathit{th}}}}$ . $ \left(\vphantom{1 - \left(\frac{x}{a}\right)^2 }\right.$1 - $ \left(\vphantom{\frac{x}{a}}\right.$$ {\frac{x}{a}}$ $ \left.\vphantom{\frac{x}{a}}\right)^{2}_{}$ $ \left.\vphantom{1 - \left(\frac{x}{a}\right)^2 }\right)$ - $ {\frac{\Delta T}{2}}$ . $ {\frac{x}{a}}$ + $ \overline{T}$ (A3)

with

$\displaystyle \Delta$T = T1 - T2,         $\displaystyle \overline{T}$ = $\displaystyle {\frac{T_{1} + T_{2}}{2}}$ (A4)
PE = H . A . 2 . a,         Gth = $\displaystyle {\frac{\kappa_{L} \cdot A}{2 \cdot a}}$   . (A5)

It consists of a linear term arising from the boundary condition and a quadratic term arising from heat generation inside the device due to the dissipated electrical power PE. The temperature distribution is shown in Fig. A.1b.

To derive a thermal equivalent circuit the discretized lattice heat flow equation as solved by MINIMOS-NT can be used. Assuming constant electrical power dissipation PE and a constant thermal heat capacity cL the expression for a grid point i reads [36]

$\displaystyle \sum_{j}^{}$Pi, j = $\displaystyle \sum_{j}^{}$$\displaystyle {\frac{P_{E}}{2}}$ + Cth . $\displaystyle {\frac{T_{L} - T_{L,o}}{\Delta t}}$ (A6)
Pi, j = Gth . $\displaystyle \left(\vphantom{ T_{i} - T_{j} }\right.$Ti - Tj$\displaystyle \left.\vphantom{ T_{i} - T_{j} }\right)$ (A7)
Cth = Vi . $\displaystyle \rho_{L}^{}$ . cL   . (A8)

The sum in (A.6) considers the contribution of all neighbor points j with Pi, j being the thermal heat flowing from point i to point j. Using heat flows instead of electrical currents and temperatures instead of voltages an electrical equivalent circuit can be used to model (A.6). This equivalent circuit is shown in Fig. A.2 for grid point i in a two-dimensional situation with four neighbor points.

Figure A.2: a) Grid point i and 4 neighbors used for the discretization of the lattice heat flow equation. b) Electrical analog circuit for the lattice heat flow equation.
\begin{figure}
\begin{center}
\resizebox{16cm}{!}{
\psfrag{a} {$\scriptstyle a)$...
...phics[width=16cm,angle=0]{figures/thermal-geo-grid.eps}}\end{center}\end{figure}

This equivalent circuit is approximately valid for the most general case. The geometry of a schematic layout is shown in Fig. A.3. To keep the problem tractable, device simulation is normally restricted to the electrical active regions which make up only a small portion of the chip. Heat generation is even further restricted to small areas of the device which normally are the space charge regions for bipolar devices and the channel regions for MOS devices. For other areas like buried collectors and substrates heat generation is normally negligible as either the electric field, the current density, or both are low. Therefore the heat generation term H can be neglected for these areas and the thermal equivalent circuit reduces to resistances and capacitances.

On the other hand, for the electrical active region the thermal resistances and capacitances are of minor importance due to their small size. This is the reason why power dissipation in electrical devices is normally modeled by a power source alone which can be considered as reducing the power source to a point source.

It is worthwhile to point out the simplifying assumptions made in the derivations above:

Figure A.3: Electrical and thermal modeling of several transistors.
\begin{figure}
\begin{center}
\resizebox{16cm}{!}{
\psfrag{Electrical Region T1}...
...phics[width=16cm,angle=0]{figures/thermal-coupling.eps}}\end{center}\end{figure}


next up previous contents
Next: B. Device Model Implementation Up: Dissertation Grasser Previous: 8. Outlook
Tibor Grasser
1999-05-31