DESSIS (Device Simulation for Smart Integrated Systems) is the device simulator of ISE AG (website: ) which is now available in version 7.5. DESSIS is a multi-dimensional simulator for simulation of one, two and three-dimensional semiconductor devices and has mixed-mode capabilities for circuit simulation. Depending on the device which is simulated and on the accuracy which is needed different transport models can be used, which are drift-diffusion, self-heating, hydrodynamic, or Monte-Carlo which is performed in a user-specified window only. DESSIS is capable to perform steady state, transient, AC-small signal, and noise analysis. Mixed mode simulations can be carried out by combining physical devices and compact models in a circuit.
Like several other simulators DESSIS does not take properties of different materials of dopands into account; it only uses net-doping concentration for simulation which is simply calculated from the doping concentration.
Several mobility models are implemented which are, for instance, mobility due to lattice scattering, mobility degradation due to impurities, degradation at the interfaces, carrier to carrier scattering, and effects due to high electric fields. DESSIS supports several models for generation/recombination processes like Shockley-Read-Hall, Auger, trap-assisted Auger, Fermi-Dirac and Boltzmann statistics, or tunneling.
DESSIS supports several materials, e.g., Si, SiGe, SiC, and III-V materials like GaAs. A physical model interface (PMI) allows user-defined model definitions for several models like generation/recombination mechanisms, impact ionization, mobility models, or carrier lifetimes.
Direct and iterative linear solvers are available. Quantum effects can be simulated using a Schrödinger solver.
The equations are discretized using the Box Integration Method. DESSIS uses both tetrahedral and hybrid grids.
Dessis has been used for simulations for three-dimensional quantum well lasers diodes . The three-dimensional RESURF (reduced surface field) Super-Junction concept has been investigated for high power diodes  and for lateral trench gate Power MOSFETs [68,69].
Fig. 1.2 shows single-event upsets (SEU)  in a n-MOS transistor of a SRAM cell which has been simulated using Dessis .
Robert Klima 2003-02-06