4.2.1 Maximum Clock in Digital Circuits

The speed of a logic block is usually measured in terms of maximum clock frequency (this applies only to synchronous circuits). It is the result of, among other factors, the sum of delay times in the critical paths. The main sources of delays are the gate switching delay and those due to distributed RC effects in interconnection lines. The maximum clock frequency is then

$$f_{clock,max}= \frac{1} {\sum\limits_{all~paths~\in~critical~path} {(t_{d,gate} + t_{d,interconnect})}}.$$ (4.5)

Figure 4.2: Ring oscillator (the number of inverting stages must be odd).

The delay time of a given logic block $t_{d,gate}$ is very difficult to quantify. It depends on the logic style, circuit techniques, the number of inputs (fan-in) and the number of loads connected (fan-out). Compact formulas estimating this delay for the most common logic style are presented in [39].

In technology development and evaluation a good method to determine the delay time is using a ring oscillator. This circuit consists of a series connection of the stages under analysis. If the stage is inverting, an odd number of them is used, and for non-inverting stages an inverter, which should be designed to present an input capacitance and delay similar to the block under analysis, is inserted into the loop.

The mostly common ring oscillator uses inverters, as shown in Figure 4.2. If $N$ is the number of stages and $t_d$ the delay time per stage, this circuit oscillates at a frequency $f_{osc}= 1/(2Nt_d)$. Measuring this frequency, the delay time is calculated by

$$t_d= \frac{1} {2\cdot N \cdot f_{osc}}.$$ (4.6)

Figure 4.3: Simplified inverter model.

This method will be used in the next chapter to characterize the performance of the technology presented there. Inverters are also well suited to investigate the main causes of delay. If we model the inverter as in Figure 4.3 we obtain

$$t_{d,gate}= \frac{C_{eq} \cdot V_{DD}}{2 \cdot \bar{I}_{on,MOS}}.$$ (4.7)

The average current in the on-state $\bar{I}_{on,MOS}$ is a function of $V_{DD}$ and technology dependent parameters. If the simple SPICE level-1 model is considered, it equals $\beta \cdot V_{DD}^2/4$ with $\beta= \mu \epsilon/t_{ox} (W/L)$ being the MOS gain factor. It was assumed that the PMOS transistor has a (W/L) adjusted to make $\bar{I}_{on,PMOS} \approx \bar{I}_{on,NMOS}$. Thus, the delay times in cases (i) and (ii) are equal.

In submicron technologies and low voltages this equation looses validity and there are no accurate close formulas. However, (4.7) is useful as it puts in evidence that $V_{DD}$ and $C_{eq}$ are first order parameters.

The interconnections contribute to the delay as well. This delay is caused by loading the active devices and by distributed RC delays (especially important for long distance lines). It means that $C_{eq}$ must be the sum of the intrinsic transistor capacitance and the parasitic capacitance of the interconnections at that node. The distributed effect is, in general, not analytically calculable as it depends on the geometry of the interconnections which may have an almost arbitrary shape. As for regular shapes the capacitance and resistance per unit length ($R$ and $C$, respectively) are constant, and an approximated delay can be calculated [40]:

$$t_{d,interconnect} \approx L_{wire}^2 C (0.4R+0.7R_{src})~~~~~~for~C_L \ll C L_{wire}$$ (4.8)

where $R_{src}$ is the resistance of the source of signal, $C_L$ the capacitance connected to the other terminal of the line and $L_{wire}$ its length.

Replacing $t_{d,gate}$ and $t_{d,interconnect}$ in (4.5) by (4.7) and (4.8) results

$$f_{clock,max}= \frac{1} {\sum\limits_{all~paths~\in~critica... ...{\bar{I}_{on,MOS}} + L_{wire}^2 C (0.4 R + 0.7 R_{src}))}}.$$ (4.9)