accurately simulated the near field of a microcontroller IC, only utilizing the currents on the package and neglecting the currents on the die. Both  and  explained that the near field of an IC can be modeled with the currents on the IC package. The near field of the IC is directly related to the IC common mode coupling to the cavity field, as presented in the previous section. Therefore, the common mode coupling of an IC can also be modeled only from the currents on the package. It is also evident that only the vertical segments of the package couple to the cavity, because these segments are large compared to the vertical interconnects on the die. An introduction of the vertical segments from the package interconnects with their associated currents according to the previously described method correctly models the coupling of the IC to the cavity. A standard ICEM model for conducted emission simulations accurately describes the currents and voltages on the package of the device. A freeware tool for ICEM modeling and further IC EMC issues has been presented by  and ICEM modeling is described in the ICEM cookbook . ICEM package modeling issues are described in . Chip level passive distribution network ICEM modeling was presented in  and dynamic IC switching current ICEM modeling was present in . Examples for accurate VLSI ICEM models have been presented by  and . The positions and lengths of the vertical package interconnects are obtained from a mechanical package drawing or from CAD data. The lengths of the vertical segments are used to obtain the associated coupling factors d/h for the introduction of the package excitation currents to the cavity model. Package coding is regulated by the JEITA  standard EIAJ ED-7303B. The package code includes information about the material of the package body, package specific features, the basic package designation, the package terminal number, the package nominal dimension, and the terminal in-line interval. Table 5.2 contains a list of some basic IC package type designations. All packages, with exception of the BGA type, are lead frame packages. The vertical segments of a lead frame package are the pins and the bond wires, while the vertical segments of a BGA package are the balls, the vias of an interposer PCB, and the vertical bond wire segments.
The package specific feature code, which is added to package designation before the basic
designation, determines, among other package properties the seated height of the package.
Table 5.3 contains a list of seated hight codes. The maximum seating
height determines the maximum possible vertical segment length of a package.
|Current flow path on the PCB, the IC package, and the die. The vertical current segments are on the pins of the leadframe and on the bond wires. The dotted current arrows indicate that the current is flowing on the lower side of the lead frame pins, according to a shorter current loop.|
|Current loops on the PCB and on the IC package. Introduction of the IC into the cavity model is performed with the vertical current segments of the package current loop at the pins of the leadframe. Median height and length values are used to model the current loop on the package. Note that the vertical bond wire segments can only be included into the median loop, when their height is low. A comparison of the simulation results, with and without explicit modeling of the vertical bond wire segments, should be made to validate the simplified package model.|
C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover