


Since the gatedelay time is proportional to the parasitic capacitance and inversely proportional to the oncurrent (5.1), there is an optimal value for the gatesource spacer length, , which minimizes the gatedelay time. The optimal value for the gatesource spacer length is achieved if
(5.6) 
The optimal gatesource spacer length for a device with zero barrier height for electrons is for and . For devices with positive barrier heights the optimal value of the gatesource spacer length is smaller than that of a device with zero barrier height due to the higher sensitivity of the oncurrent with respect to the gatesource spacer length.
Note that the optimal value for depends on . For small values of the gatedrain parasitic capacitance dominates the gatesource parasitic capacitance. Therefore, any further decrease of the gatesource spacer length does not improve the gatedelay time. As shown in Fig. 5.16, the optimal value of the gatesource spacer length for the given material and geometrical parameters results in optimized device characteristics.
M. Pourfath: Numerical Study of Quantum Transport in Carbon NanotubeBased Transistors