5.3.2 Optimized Spacer Length

In Section 5.2.1 it was shown that by increasing the gate-source spacer length the parasitic capacitance between these two contacts is reduced, and so does the on-current. In Section 5.2.2 it was shown that by increasing the gate-drain spacer length the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio increases. At the same time, by increasing the gate-drain spacer length the parasitic capacitance between these two contacts decreases, which results in a reduced gate-delay time. Fig. 5.14 shows the effect of the gate-drain spacer length on the gate-delay time versus the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio, which indicates a significant performance improvement by increasing the gate-drain spacer length.

Figure 5.14: The effect of $L_\textrm {GD}$ on the gate-delay time versus the $I_\mathrm{on}$/ $I_\mathrm{off}$ ratio for a device with zero barrier height for electrons (q $\Phi _\textrm {Be}$=0). $L_\textrm {GS}$ = 2 nm and $V_\textrm {D}$ = 0.8 V.

Figure 5.15: The sensitivity of the parasitic capacitance and the on-current with respect to $L_\textrm {GS}$ for a device with a) zero barrier height (q $\Phi _\textrm {Be}$ = 0) and b) positive barrier height (q $\Phi _\textrm {Be}$ = 0.3 eV) for electrons. The intersection of the curves gives the optimum $L_\textrm {GS0}$ which minimizes $\tau$.

Figure 5.16: The effect of $L_\textrm {GS}$ on the gate-delay time versus the $I_\textrm {on}$/ $I_\textrm {off}$ ratio for a device with zero barrier height for electrons (q $\Phi _\textrm {Be}$ = 0). $V_\textrm {D}$ = 0.8 V. The optimal $L_\textrm {GS}$ for both device types are shown.

Since the gate-delay time is proportional to the parasitic capacitance and inversely proportional to the on-current (5.1), there is an optimal value for the gate-source spacer length, $\mathrm{L_{GS0}}$, which minimizes the gate-delay time. The optimal value for the gate-source spacer length is achieved if

$${\frac{\partial \tau}{\partial L_\mathrm{GS}}}\Big\arrowvert_\mat... ...l I_\mathrm{on}}{\partial L_\mathrm{GS}}\Big\arrowvert_\mathrm{L_{GS0}} = 0 \ .$$ (5.6)

Fig. 5.15 shows the sensitivity of the on-current with respect to the gate-source spacer length for devices with zero and positive barrier heights for electrons. For thinner insulators the width of the source-sided barrier decreases, resulting in a higher tunneling current contribution to the total current and a higher sensitivity of the on-current to $L_\mathrm{GS}$ (see Section 5.2.1).

The optimal gate-source spacer length for a device with zero barrier height for electrons is $L_\mathrm{GS}\mathrm{\approx 6~nm}$ for $T_\mathrm{Ins}=\mathrm{2~nm}$ and $L_\mathrm{GD}=\mathrm{20~nm}$. For devices with positive barrier heights the optimal value of the gate-source spacer length is smaller than that of a device with zero barrier height due to the higher sensitivity of the on-current with respect to the gate-source spacer length.

Note that the optimal value for $L_\mathrm{GS}$ depends on $L_\mathrm{GD}$. For small values of $L_\mathrm{GD}$ the gate-drain parasitic capacitance dominates the gate-source parasitic capacitance. Therefore, any further decrease of the gate-source spacer length does not improve the gate-delay time. As shown in Fig. 5.16, the optimal value of the gate-source spacer length for the given material and geometrical parameters results in optimized device characteristics.

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