5.3.1 Gate-Delay Time of CNT-FETs

The total gate capacitance is given by , where and are the gate-source and gate-drain parasitic capacitances, and can be written as , where is the gate insulator capacitance and is the so called

where is the electrostatic potential on the surface of the CNT and is the total charge along the CNT. Given the one-dimensional density of states and assuming equilibrium conditions, (5.2) can be approximated as[265,264,266]

where the twofold band and spin degeneracy is included. If thin and high- insulators are used, then and , implying that the potential on the CNT becomes equal to the gate potential (perfect coupling). This regime is called

where is the gate insulator thickness and is the radius of the CNT. Assuming a gate insulator with a thickness of , , satisfying the condition of the quantum capacitance limit ( ). Parasitic capacitances are usually much larger than the quantum capacitance ( ) [268,269]. Therefore, the gate capacitance can be approximated as

(5.5) |