5.3.1 Gate-Delay Time of CNT-FETs

The gate-delay time, which characterizes the switching response of the transistor, is an important metric for digital electronic applications. The gate-delay time of a transistor is defined as time taken to charge a constant gate capacitance $ C_\mathrm{G}$ to a voltage $ V_\mathrm{DD}$ at a constant current $ I_\mathrm{on}$

\begin{displaymath}\begin{array}{l}\displaystyle \tau \ = \ \frac{C_\mathrm{G} \ V_\mathrm{DD}}{I_\mathrm{on}} \ . \end{array}\end{displaymath} (5.1)

The total gate capacitance is given by $ C_\mathrm{G}=C_\mathrm{GG}+
C_\mathrm{GS}+C_\mathrm{GD}$, where $ C_\mathrm{GS}$ and $ C_\mathrm{GD}$ are the gate-source and gate-drain parasitic capacitances, and $ C_\mathrm{GG}$ can be written as $ C^{-1}_\mathrm{G} = {C_\mathrm{Ins}}^{-1} +
{C_\mathrm{CNT}}^{-1}$, where $ C_\mathrm{Ins}$ is the gate insulator capacitance and $ C_\mathrm{Q}$ is the so called quantum capacitance given by [264]

\begin{displaymath}\begin{array}{l}\displaystyle C_\mathrm{Q} \ = \ \frac{\partial Q_\mathrm{CNT}}{\partial \phi_\mathrm{CNT}} \ , \end{array}\end{displaymath} (5.2)

where $ \phi_\mathrm{CNT}$ is the electrostatic potential on the surface of the CNT and $ Q_\mathrm{CNT}$ is the total charge along the CNT. Given the one-dimensional density of states and assuming equilibrium conditions, (5.2) can be approximated as[265,264,266]

\begin{displaymath}\begin{array}{l}\displaystyle C_\mathrm{Q} \ \approx \ \frac{...
...athrm{F}}\approx 400~\mathrm{aF}/\mathrm{\mu m} \ , \end{array}\end{displaymath} (5.3)

where the twofold band and spin degeneracy is included. If thin and high-$ \kappa$ insulators are used, then $ C_\mathrm{Ins}\gg C_\mathrm{Q}$ and $ C_\mathrm{GG}\approx C_\mathrm{Q}$, implying that the potential on the CNT becomes equal to the gate potential (perfect coupling). This regime is called quantum capacitance limit in which the device is potential-controlled rather than charge-controlled [267]. The insulator capacitance, occurring between the CNT and a cylindrical gate, is given by

\begin{displaymath}\begin{array}{l}\displaystyle C_\mathrm{Ins} = \frac{2\pi\kap...
...}}{\mathrm{ln}(T_\mathrm{Ins}/R_\mathrm{CNT}+1)} \ ,\end{array}\end{displaymath} (5.4)

where $ T_\mathrm{Ins}$ is the gate insulator thickness and $ R_\mathrm{CNT}$ is the radius of the CNT. Assuming a $ \mathrm{HfO_2}$ gate insulator with a thickness of $ 2~\mathrm{nm}$, $ C_\mathrm{Ins}\mathrm{\approx 1500 aF/{{\mu}m}}$, satisfying the condition of the quantum capacitance limit ( $ C_\mathrm{Q}\ll
C_\mathrm{Ins}$). Parasitic capacitances are usually much larger than the quantum capacitance ( $ C_\mathrm{GS}+C_\mathrm{GD}\gg
C_\mathrm{Q}$) [268,269]. Therefore, the gate capacitance can be approximated as

\begin{displaymath}\begin{array}{l}\displaystyle C_\mathrm{G} \approx {C_\mathrm{GS}+C_\mathrm{GD}} \ . \end{array}\end{displaymath} (5.5)

M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors