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D. Adalsteinsson and J.A. Sethian,
``A Fast Level Set Method for Propagating Interfaces,''
J.Comput.Phys., vol. 118, no. 1, pp. 269-277, 1995.

D. Adalsteinsson and J.A. Sethian,
``Level Set Methods for Etching, Deposition and Photolithography Development,''
IEEE J.Technology Computer Aided Design, 1997,

M. Armacost, P.D. Hoh, R. Wise, W. Yan, J.J. Brown, J.H. Keller, G.A. Kaplita, S.D. Halle, K.P. Muller, M.D. Naeem, S. Srinivasan, H.Y. Ng, M. Gutsche, A. Gutmann, and B. Spuler,
``Plasma-Etching Processes for ULSI Semiconductor Circuits,''
IBM J.Res.Dev., vol. 43, no. 1/2, pp. 39-72, 1999.

D.S. Bang, Z. Krivokapic, M. Hohmeyer, J.P. McVittie, and K.C. Saraswat,
``Three Dimensional Simulation for Sputter Deposition Equipment and Process,''
In H. Ryssel and P. Pichler, editors, Simulation of Semiconductor Devices and Processes, vol. 6, pp. 166-169, Springer, Wien, 1995.

R.E. Bank,
PLTMG: A Software Package for Solving Elliptic Partial Differential Equations,
vol. 15 of Frontiers in Applied Mathematics,
SIAM, Philadelphia, 1994
Users' Guide 7.0.

E. Bär and J. Lorenz,
``3-D Simulation of LPCVD Using Segment-Based Topography Discretization,''
IEEE Trans.Semiconductor Manufacturing, vol. 9, no. 1, pp. 67-73, 1996.

J.P. Chang, A.P. Mahorowala, and H.H. Sawin,
``Plasma-Surface Kinetics and Feature Profile Evolution in Chlorine Etching of Polysilicon,''
J.Vac.Sci.Technol.A, vol. 16, no. 1, pp. 217-224, 1998.

D.R. Cote, S.V. Nguyen, A.K. Stamper, D.S. Armbrust, D. Többen, R.A. Conti, and G.Y. Lee,
``Plasma-Assisted Chemical Vapor Deposition of Dielectric Thin Films for ULSI Semiconductor Circuits,''
IBM J.Res.Dev., vol. 43, no. 1/2, pp. 5-38, 1999.

F.H. Dill,
``Optical Lithography,''
IEEE Trans.Electron Devices, vol. 22, no. 7, pp. 440-444, 1975.

F.H. Dill, A.R. Neureuther, J.A. Tuttle, and E.J. Walker,
``Modeling Projection Printing of Positive Photoresists,''
IEEE Trans.Electron Devices, vol. 22, no. 7, pp. 456-464, 1975.

G.A. Dixit, C.C. Wei, F.T. Liou, and H. Zhang,
``Reactively Sputtered Titanium Nitride Films for Submicron Contact Barrier Metallization,''
Appl.Phys.Lett., vol. 62, no. 4, pp. 357-359, 1993.

Y. Eguchi, M.M IslamRaja, J.P. McVittie, and K.C Saraswat,
``Profile Modeling of Physical Vapor Deposition of Ti and WSi$_x$,''
In Symp. on Process Physics and Modeling in Semicond.Technol., pp. 301-309, 1993.

C. Eisenmenger-Sittner, R. Beyerknecht, A. Bergauer, W. Bauer, and G. Betz,
``Angular-Distribution of Sputtered Neutrals in a Post Magnetron Geometry - Measurement and Monte-Carlo Simulation,''
J.Vac.Sci.Technol.A, vol. 13, no. 5, pp. 2435-2443, 1995.

M. Eizenberg,
``Chemical Vapor Deposition of TiN for Sub-0.5 $\mu $m ULSI Circuits,''
MRS Bulletin, vol. 20, no. 11, pp. 38-41, 1995.

C. Faltermeier, C. Goldberg, M. Jones, A. Upham, D. Manger, G. Peterson, J. Lau, A.E. Kaloyeros, B. Arkles, and A. Paranjpe,
``Barrier Properties of Titanium Nitride Films Grown by Low Temperature Chemical Vapor Deposition from Titanium Tetraiodide,''
J.Electrochem.Soc., vol. 144, no. 3, pp. 1002-1008, 1997.

P. Fleischmann,
Mesh Generation for Technology CAD in Three Dimensions,
Dissertation, Technische Universität Wien, 1999.

P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr,
``Grid Generation for Three Dimensional Process and Device Simulation,''
In Simulation of Semiconductor Processes and Devices, pp. 161-166, Business Center for Academic Societies Japan, Tokyo, Japan, 1996.

M. Fujinaga and N. Kotani,
``3-D Topography Simulator (3-D MULSS) Based on a Physical Description of Material Topography,''
IEEE Trans.Electron Devices, vol. 44, no. 2, pp. 226-238, 1997.

C.R. Giardina and E.R. Dougherty,
Morphological Methods in Image and Signal Processing,
Prentice-Hall, New Jersey, 1988.

S. Hamaguchi, M. Dalvie, R.T. Farouki, and S. Sethuraman,
``A Shock-tracking Algorithm for Surface Evolution under Reactive-Ion Etching,''
J.Appl.Phys., vol. 74, no. 8, pp. 5172-5184, 1993.

S. Hamaguchi and S.M. Rossnagel,
``Simulation of Trench-Filling Profiles under Ionized Magnetron Sputter Metal Deposition,''
J.Vac.Sci.Technol.B, vol. 13, no. 2, pp. 183-191, 1995.

S. Hamaguchi and S.M. Rossnagel,
``Liner Conformality in Ionized Magnetron Sputter Metal Deposition Process,''
J.Vac.Sci.Technol.B, vol. 14, no. 4, pp. 2603-2608, 1996.

U. Hansen, P. Vogl, and V. Fiorentini,
``Atomistic Modeling of Large-Scale Metal Film Growth Fronts,''
Physical Review B, vol. 59, no. 12, pp. 7856-7859, 1999.

J.H. Helmsen and A.R. Neureuther,
``3D Lithography Cases for Exploring Technology Solutions and Benchmarking Simulators,''
In Proc. SPIE Optical/Laser Microlithography VI, vol. 1927, pp. 382-394, 1993.

R.J. Hoekstra, M.J. Grapperhaus, and M.J. Kushner,
``Integrated Plasma Equipment Model for Polysilicon Etch Profiles in an Inductively Coupled Plasma Reactor with Subwafer and Superwafer Topography,''
J.Vac.Sci.Technol.A, vol. 15, no. 4, pp. 1913-1921, 1997.

R.J. Hoekstra and M.J. Kushner,
``Comparison of Two-dimensional and Three-dimensional Models for Profile Simulation of Poly-Si Etching of Finite Length Trenches,''
J.Vac.Sci.Technol.A, vol. 16, no. 6, pp. 3274-3280, 1998.

Z.-K. Hsiau, E.C. Kan, J.P. McVittie, and R.W. Dutton,
``Robust, Stable, and Accurate Boundary Movement for Physical Etching and Deposition Simulation,''
IEEE Trans.Electron Devices, vol. 44, no. 9, pp. 1375-1385, 1997.

P. Kapur, D.S. Bang, J.P. McVittie, K.C. Saraswat, and T. Mountsier,
``Method for Angular Sputter Yield Extraction for High-Density Plasma Chemical Vapor Deposition Simulators,''
J.Vac.Sci.Technol.B, vol. 16, no. 3, pp. 1123-1128, 1998.

D.J. Kim, W.G. Oldham, and A.R. Neureuther,
``Development of Positive Photoresist,''
IEEE Trans.Electron Devices, vol. 31, no. 12, pp. 1730-1736, 1984.

E.J. Kim and W.N. Gill,
``Modeling of CVD of Silicon Dioxide Using TEOS and Ozone in a Single-Wafer Reactor,''
J.Electrochem.Soc., vol. 141, no. 12, pp. 3462-3472, 1994.

H. Kirchauer,
Photolithography Simulation,
Dissertation, Technische Universität Wien, 1998.

H. Kirchauer and S. Selberherr,
``Rigorous Three-Dimensional Photoresist Exposure and Development Simulation over Nonplanar Topography,''
IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 12, pp. 1431-1438, 1997.

H. Kirchauer and S. Selberherr,
``Three-Dimensional Photolithography Simulator Including Rigorous Nonplanar Exposure Simulation for Off-Axis Illumination,''
In Proc. SPIE Optical Microlithography XI, vol. 3334, pp. 764-776, 1998.

H. Liao and T.S. Cale,
``Three-dimensional Simulation of an Isolation Trench Refill Process,''
Thin Solid Films, vol. 236, no. 1-2, pp. 352-358, 1993.

H. Liao and T.S. Cale,
``Low-Knudsen-Number Transport and Deposition,''
J.Vac.Sci.Technol.A, vol. 12, no. 4, pp. 1020-1026, 1994.

A. Liu and M. Horlacher,
``Tracking the Front of Moving Boundaries Using Grid Generation Techniques,''
In 8th International Meshing Roundtable, pp. 333-343, South Lake Tahoe, CA, October 1999.

D. Liu, S.K. Dew, M.J. Brett, T. Janacek, T. Smy, and W. Tsai,
``Experimental Study and Computer Simulation of Collimated Sputtering of Titanium Thin Films over Topographical Features,''
J.Appl.Phys., vol. 74, no. 2, pp. 1339-1344, 1993.

W.E. Lorensen and H.E. Cline,
``Marching Cubes: A High Resolution 3D Surface Construction Algorithm,''
Computer Graphics, vol. 21, no. 4, pp. 163-169, 1987.

J. Lorenz, B. Baccus, and W. Henke,
``Three-Dimensional Process Simulation,''
Microelectronic Engineering, vol. 34, no. 1, pp. 85-100, 1996.

A. Malaurie and A. Bessaudou,
``Numerical-Simulation of the Characteristics of the Different Metallic Species Falling on the Growing Film in DC Magnetron Sputtering,''
Thin Solid Films, vol. 286, no. 1-2, pp. 305-316, 1996.

R. Martins,
On the Design of Very Low Power Integrated Circuits,
Dissertation, Technische Universität Wien, 1999.

R. Martins and S. Selberherr,
``Layout Data in TCAD Frameworks,''
In Modelling and Simulation, pp. 1122-1126. Society for Computer Simulation International, 1996.

E.J. McInerney, T.W. Mountsier, and E.K. Broadbent,
``A New Analytic Rate Expression for Hydrogen Reduced Tungsten,''
In Conference Proceedings ULSI-VIII, pp. 161-167, Materials Research Society, 1993.

A. Misaka and K. Harafuji,
``Simulation Study of Micro-Loading Phenomena in Silicon Dioxide Hole Etching,''
IEEE Trans.Electron Devices, vol. 44, no. 5, pp. 751-760, 1997.

G.E. Moore,
``Cramming More Components onto Integrated Circuits,''
Electronics, pp. 114-117, 1965.

A.M. Myers, J.R. Doyle, and J.R. Abelson,
``Monte Carlo Simulations of Magnetron Sputtering Particle Transport,''
J.Vac.Sci.Technol.A, vol. 9, no. 3, pp. 614-618, 1991.

A.M. Myers, J.R. Doyle, and D.N. Ruzic,
``Monte Carlo Simulations of Sputter Atom Transport in Low-Pressure Sputtering: The Effects of Interaction Potential, Sputter Distribution, and System Geometry,''
J.Appl.Phys., vol. 72, no. 7, pp. 3064-3071, 1992.

K. Nanbu, S. Uchida, and H. Yoshida,
``Computer-Simulation of Growth of Thin-Films Fabricated by the Sputtering Method - Comparison with Experiment,''
Thin Solid Films, vol. 228, no. 1-2, pp. 330-332, 1993.

H.J. Oh, S.W. Rhee, and I.S. Kang,
``Simulation of CVD Process by Boundary Integral Technique,''
J.Electrochem.Soc., vol. 139, no. 6, pp. 1714-1720, 1992.

W.G. Oldham, A.R. Neureuther, C. Sung, J.L. Reynolds, and S.N. Nandgaonkar,
``A General Simulator for VLSI Lithography and Etching Processes: Part II-Application to Deposition and Etching,''
IEEE Trans.Electron Devices, vol. 27, no. 8, pp. 1455-1459, 1980.

Y.H. Park, A.H. Chung, and M.A. Ward,
``Step Coverage Evaluation of Copper Films Prepared by Magnetron Sputtering,''
In VLSI Multilevel Interconnection Conf., pp. 295-297, IEEE, Santa Clara, CA, 1991.

J. Pelka,
``Three-Dimensional Simulation of Ion-Enhanced Dry-Etch Processes,''
Microelectronic Engineering, vol. 14, no. 3-4, pp. 269-281, 1991.

P.L. O'Sullivan, F.H. Baumann, and G.H. Gilmer,
``Numerical Simulations of Sputter Deposition and Etching in Trenches using the Level Set Technique,''
In Proc. 2nd Int. Conf. on Modeling and Simulation of Microsystems, pp. 449-451, San Juan, Puerto Rico, USA, 1999.

R. Plasun, M. Stockinger, and S. Selberherr,
``Integrated Optimization Capabilities in the VISTA Technology CAD Framework,''
IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1244-1251, 1998.

M. Radi,
``Simulation der Diffusion mit zellularen Automaten,''
Diplomarbeit, Technische Universität Wien, 1994.

M. Radi, E. Leitner, and S. Selberherr,
``AMIGOS: Analytical Model Interface & General Object-Oriented Solver,''
IEEE J.Technology Computer Aided Design, 1999,

N. Rohrer, C. Akrout, M. Canada, D. Cawthron, B. Davari, R. Floyd, S. Geissler, R. Goldblatt, R. Houle, P. Kartschoke, D. Kramer, P. McCormick, G. Salem, R. Schulz, L. Su, and L. Whitney,
``A 480MHz RISC Microprocessor in a 0.12$\mu $m L $_{\mathit{eff}}$ CMOS Technology with Copper Interconnects,''
In IEEE Int. Solid-State Circuits Conference, pp. 240-241, 1998.

S.M. Rossnagel and J. Hopwood,
``Metal Ion Deposition from Ionized Magnetron Sputtering Discharge,''
J.Vac.Sci.Technol.B, vol. 12, no. 1, pp. 449-453, 1994.

D.N. Ruzic,
``The Effects of Surface Roughness Characterized by Fractal Geometry on Sputtering,''
Nuclear Instruments and Methods in Physics Research, vol. B47, no. 2, pp. 118-125, 1990.

D.N. Ruzic and H.K. Chiu,
``Modeling of Particle-Surface Reflections Including Surface Roughness Characterized by Fractal Geometry,''
Journal of Nuclear Materials, vol. 162-164 pp. 904-909, 1989.

J.G. Ryan, S.B. Brodsky, T. Katata, M. Honda, N. Shoda, and H. Aochi,
``Collimated Sputtering of Titanium and Titanium Nitride Films,''
MRS Bulletin, vol. 20, no. 11, pp. 42-45, 1995.

R. Sabelka and S. Selberherr,
``SAP -- A Program Package for Three-Dimensional Interconnect Simulation,''
In Proc. Intl. Interconnect Technology Conference, pp. 250-252, Burlingame, California, 1998.

R.R. Schaller,
``Moore's Law: Past, Present, and Future,''
IEEE Spectrum, vol. 34, no. 6, pp. 53-59, 1997.

E.W. Scheckler,
Algorithms for three-dimensional simulation of etching and deposition processes in integrated circuit fabrication,
Dissertation, University of California, Berkeley, 1991.

E.W. Scheckler and A.R. Neureuther,
``Models and Algorithms for Three-Dimensional Topography Simulation with SAMPLE-3D,''
IEEE Trans.Computer-Aided Design, vol. 13, no. 2, pp. 219-230, 1994.

W.J. Schroeder, J.A. Zarge, and W.E. Lorenson,
``Decimation of Triangle Meshes,''
Computer Graphics, vol. 26, no. 2, pp. 65-70, 1992.

Semiconductor Industry Association,
The National Technology Roadmap for Semiconductors,

J.A. Sethian and D. Adalsteinsson,
``An Overview of Level Set Methods for Etching, Deposition, and Lithography Development,''
IEEE Trans.Semiconductor Manufacturing, vol. 10, no. 1, pp. 167-184, 1997.

M.K. Sheergar, T. Smy, S.K. Dew, and M.J. Brett,
``Simulation of Three-dimensional Refractory Metal Step Coverage over Contact Cuts and Vias,''
J.Vac.Sci.Technol.B, vol. 14, no. 4, pp. 2595-2602, 1996.

Jonathan Richard Shewchuk,
``Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator,''
In Ming C. Lin and Dinesh Manocha, editors, Applied Computational Geometry: Towards Geometric Engineering, vol. 1148 of Lecture Notes in Computer Science, , pp. 203-222, Springer-Verlag, 1996
From the First ACM Workshop on Applied Computational Geometry.

T. Smy, S.K. Dew, and M.J. Brett,
``Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization,''
MRS Bulletin, vol. 20, no. 11, pp. 65-69, 1995.

T. Smy, L. Tan, K. Chan, R.N. Tait, J.N. Broughton, S.K. Dew, and M.J. Brett,
``A Simulation Study of Long Throw Sputtering for Diffusion Barrier Deposition into High Aspect Vias and Contacts,''
IEEE Trans.Electron Devices, vol. 45, no. 7, pp. 1414-1425, 1998.

E. Strasser,
Simulation von Topographieprozessen in der Halbleiterfertigung,
Dissertation, Technische Universität Wien, 1994.

E. Strasser, G. Schrom, K. Wimmer, and S. Selberherr,
``Accurate Simulation of Pattern Transfer Processes Using Minkowski Operations,''
IEICE Trans.Electron., vol. E77-C, no. 2, pp. 92-97, 1994.

E. Strasser and S. Selberherr,
``Algorithms and Models for Cellular Based Topography Simulation,''
IEEE Trans.Computer-Aided Design, vol. 14, no. 9, pp. 1104-1114, 1995.

R. Strasser,
Rigorous TCAD Investigations on Semiconductor Fabrication Technology,
Dissertation, Technische Universität Wien, 1999.

V. Sukharev, K. Kumar, and E.J. McInerney,
``An Integrated Simulation of Across-Wafer Uniformity in Ti/TiN/W Plug-Fill,''
In Proc. of the 15th International VLSI Multilevel Interconnection Conference, pp. 306-311, Santa Clara, CA, 1998.

D.S. Taylor, M.J. Jain, and T.S. Cale,
``Deposition Rate Dependence of Step Coverage of Sputter Deposited Aluminum-(1.5%) Copper Films,''
J.Vac.Sci.Technol.A, vol. 16, no. 5, pp. 3123-3126, 1998.

S. Tazawa, K. Ochiai, S. Matsuo, and S. Nakajima,
``A High-Speed 2-D Topography Simulator Based on a Pixel Model,''
IEEE Trans.Computer-Aided Design, vol. 16, no. 4, pp. 386-397, 1997.

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``Algorithms for Simulation of Three-Dimensional Etching,''
IEEE Trans.Computer-Aided Design, vol. 13, no. 5, pp. 616-624, 1994.

S. Yamamoto, T. Kure, M. Ohgo, T. Matsuzama, S. Tachi, and H. Sunami,
``A Two-Dimensional Etching Profile Simulator: ESPRIT,''
IEEE Trans.Computer-Aided Design, vol. CAD-6, no. 3, pp. 417-422, 1987.

N. Yamauchi, T. Yachi, and T. Wada,
``A Pattern Edge Profile Simulation for Oblique Ion Milling,''
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W. Pyka: Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing