4.2.2.2 The Parasitic Capacitances, Inductances and Parasitic Line Delay

The capacitance ${\it C}_{\mathrm {IN}}$ is positioned in parallel to ${\it C}_{\mathrm{gs}}$, as well as ${\it C}_{\mathrm {OUT}}$ is parallel to ${\it C}_{\mathrm{ds}}$, and ${\it C}_{\mathrm{pgd}}$ parallel to ${\it C}_{\mathrm{gd}}$. To separate the parasitic capacitances open structures for the given layout are measured for various gate widths, where the inner transistor is physically removed. Alternatively a measurement of a transistor in pinch-off is used [36]. Using the values for the parasitic $C_i$ and measuring a short structure, the metal parts of ${\it R}_{\mathrm{G}}$ and ${\it R}_{\mathrm{D}}$ can be determined from the S-parameters as well as the parasitic inductances $L_i$. Alternatively, the determination of the $L_i$ can be replaced by forward measurements of a HEMT at ${\it V}_{\mathrm{DS}}$= 0 V at different current levels [36]. A gate width dependent port extension ${\it\tau}_{\mathrm{port}}$  is added to account for the delay of a coplanar line which additionally is part of the transistor layout in the measurement. For overall justification Fig. 4.1 and the examples in Chapter 7 show the comparison of simulation and extraction.