The capacitance is positioned in parallel to , as well as is parallel to , and parallel to . To separate the parasitic capacitances open structures for the given layout are measured for various gate widths, where the inner transistor is physically removed. Alternatively a measurement of a transistor in pinch-off is used . Using the values for the parasitic and measuring a short structure, the metal parts of and can be determined from the S-parameters as well as the parasitic inductances . Alternatively, the determination of the can be replaced by forward measurements of a HEMT at = 0 V at different current levels . A gate width dependent port extension is added to account for the delay of a coplanar line which additionally is part of the transistor layout in the measurement. For overall justification Fig. 4.1 and the examples in Chapter 7 show the comparison of simulation and extraction.