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4.1.1 The Basic Model

For MESFETs and HEMTs the well known intrinsic eight-element small-signal equivalent circuit is shown in Fig. 4.1, as published in [36]. The extraction of parasitic elements from measurements is performed according to standard procedures [36,230] which are described below. Contrary to the classical separation of the intrinsic device and the parasitic environment, Fig. 4.1 additionally shows a simulator shell, which includes the intrinsic shell and the parasitic resistances. This is useful as the semiconductor contributions to the resistances are a genuine part of the simulation domain. However, parasitic capacitances and inductances can better be obtained from gate width dependent measurements, so that they are considered extrinsic for the physical simulation. Extended equivalent circuits were suggested, e.g. by  [230] to include leakage and impact ionization phenomena in InAlAs/InGaAs based HEMTs.

Figure 4.1: Standard small-signal equivalent circuit of a HEMT [36].

\includegraphics[width=10 cm]{D:/Userquay/Promotion/HtmlDiss/fig3.eps}
Figure 4.2: Extended small-signal equivalent circuit for a HEMT including gate-leakage and impact ionization [230].
\includegraphics[width=10 cm]{D:/Userquay/Promotion/HtmlDiss/fig4.eps}

Fig. 4.2 shows an extended equivalent circuit for a mm-wave HEMT. In the input circuit two resistances $ {\it R}_{\mathrm{pgs}}$ and $ {\it R}_{\mathrm{pgd}}$ are added to account for the gate leakage. In the output circuit three additional elements are added: $ {\it g}_{\mathrm{m im}}$ introduces a $ {\it V}_{\mathrm{DS}}$ dependent contribution to $ {\mit g}_{\mathrm{m}}$ due to impact ionization and the combination of $ {\it C}_{\mathrm {im}}$ and $ {\it R}_{\mathrm{im}}$ present an additional time constant explained below. Genetic algorithms were suggested in [230] to determine small-signal equivalent elements, and are also used in this work. This circuit, usually applied for noise modeling, is used to extract breakdown information from measured S-parameters at high  $ {\it V}_{\mathrm{DS}}$ bias in combination with standard procedures. In a one-dimensional linear charge control model, as given in [23], the transconductance $ {\mit g}_{\mathrm{m}}$ is described as:

    $\displaystyle {\mit g}_{\mathrm{m}} = \frac{ {\it\varepsilon}_\mathrm{r} \cdot ...
...aystyle 1+\bigg(\frac{{\it n}_{\mathrm{c}}}{{\it n}_{\mathrm{sheet}}}\bigg)^2}}$ (4.1)

where $ {\it\varepsilon}_\mathrm{r}$ is the relative dielectric constant, $ {\it v}_{\mathrm{eff}}$ the effective carrier velocity, $ {\it W}_{\mathrm{g}}$ the gate width, and $ {\it d}_\mathrm{eff}$ an effective gate-to-channel separation. $ {\it n}_{\mathrm{sheet}}$ is the sheet charge density and $ {\it n}_{\mathrm{c}}$ a reference sheet concentration defined as:
    $\displaystyle {\it n}_{\mathrm{c}} = \frac{E_{crit} \cdot {\it l}_{\mathrm{g}} \cdot c_0}{q}$ (4.2)

with: $ E_{crit}$ is a critical field for the onset of a "saturated" behavior and $ c_0$ is an effective channel capacity assuming a fixed distance between channel charge and gate in a simple capacitor model.

As can be seen from (4.1), both a relatively higher sheet density $ {\it n}_{\mathrm{sheet}}$ and a higher effective carrier $ {\it v}_{\mathrm{eff}}$ velocity lead to higher $ {\mit g}_{\mathrm{m}}$. This explains the differences of the material systems AlGaAs/InGaAs and InAlAs/InGaAs. As an example, InAlAs/InGaAs transistors have both a higher sheet density and higher effective carrier velocities than AlGaAs/InGaAs HEMTs. Furthermore, the difference of DC- and RF- $ {\mit g}_{\mathrm{m}}$ can be explained due carrier generation/recombination resulting in changes of $ {\it n}_{\mathrm{sheet}}$. Neither velocity saturation nor parasitic charge modulation are included in this model. Describing velocity saturation a term called modulation efficiency (ME) can be derived writing an intrinsic delay time $ {\it\tau}_{\mathrm{i}}$  as:

    $\displaystyle \tau_i = \frac{{\it C}_{\mathrm{g}}}{{\mit g}_{\mathrm{m}}} =  \f...
...l}_{\mathrm{g}} +L_\mathrm {od}}{{\it v}_{\mathrm{eff}}}\cdot\frac{1}{{\it ME}}$ (4.3)

with $ {\it C}_{\mathrm{g}}$ the total gate-charge. Adding to the purely one-dimensional approach of (4.3), the effects of an additional $ {\it V}_{\mathrm{DS}}$ bias, i.e., a the two-dimensional consideration, are included using an extension of the symmetric space charge region by a length $ L_\mathrm {od}$. This length describes the drain side extension of the space charge region. Parasitic charge modulation is further included by setting an upper limit towards the modulation efficiency ME. The model assumes a saturated effective carrier velocity $ {\it v}_{\mathrm{eff}}$, with no changes as a function of $ {\it V}_{\mathrm{DS}}$. The $ {\it V}_{\mathrm{DS}}$ dependence of the carrier velocities is to be understood by two-dimensional device simulation.

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