| 1D | One dimensional |
|---|---|
| 2.5D | Two and a half dimensional |
| 2D | Two dimensional |
| 3D | Three dimensional |
| BEOL | Back end of line |
| CAD | Computer aided design |
| CMOS | Complementary metal oxide semiconductor |
| CPU | Central processing unit |
| DE | Differential equation |
| FEM | Finite element method |
| FEOL | Front end of line |
| IC | Integrated circuit |
| IMC | Intermetallic compound |
| MTTF | Mean-time-to-failure |
| NoC | Network on chip |
| PDE | Partial differential equation |
| PoP | Package on package |
| P | Packaging |
| RDL | Redistribution layer |
| SIC | Stacked integrated circuit |
| SiP | System in package |
| SoC | System on chip |
| SOI | Silicon on insulator |
| SSI | Small scale integration |
| TCAD | Technology computer aided design |
| TSV | Through silicon via |
| TTF | Time-to-failure |
| UBM | Under bump metallization |
| ULSI | Ultra large scale integration |
| VLSI | Very large scale integration |
| WLP | Wafer level packaging |