3.3.8 Application

To obtain the raw device data MINIMOS [27] is used as device simulator and the device structures can be generated either by coupled process simulation, or with an additional program from analytical profile descriptions.

Table 3.6 shows results from a pocket-implanted LDD NMOS device with $\ensuremath{L_{\mathit{nom}}}\xspace = 0.18$$\mu$m, $\ensuremath{t_{\mathit{ox}}}\xspace = 5$nm, and $\ensuremath{X_{\mathit{j}}}\xspace = 0.09$$\mu$m designed for operation at $\ensuremath{V_{\mathit{DD}}}\xspace = 1.5$V. The system parameters used for analysis were $\ensuremath{{\mathit{ld}}}\xspace = 7$ and $\ensuremath{{\mathit{ar}}}\xspace = 0.1$ (interconnect capacitances were not considered). The evaluation was carried out for the nominal case ``nominal'' and two worst-case corners (``a'': $\ensuremath{T}\xspace =\ensuremath{T_{\mathit{max}}}\xspace =125$$^{\circ }$C, channel and pocket implant doses, and $\ensuremath{L}\xspace$ reduced by 20%; and ``b'': $\ensuremath{T}\xspace =\ensuremath{T_{\mathit{min}}}\xspace =0$$^{\circ }$C, channel and pocket implant doses increased by 50%, and $\ensuremath{L}\xspace$ increased by 20%). The data ``c'' are the same as ``a'' except that $\ensuremath{t_{\mathit{ox}}}\xspace$ was reduced instead of the channel and pocket implants (to obtain the same shift in $\ensuremath{V_{\mathit{T,lin}}}\xspace$). Each of these evaluations takes a CPU time of about 5 minutes on an HP735 workstation. The errors of the inverter gain and noise margins determined from device-level simulations of an inverter are typically in the order of 5%.

Table 3.6: Performance of a pocket-implanted LDD NMOST ( $\ensuremath {L}\xspace =\rm0.18\mu m$, $\ensuremath{V_{\mathit{DD}}}\xspace =\rm1.5V$)

case	$\ensuremath{V_{\mathit{T,lin}}}\xspace$	$\ensuremath{t_{\mathit{d}}}\xspace$ 1	$\ensuremath{E_{\mathit{s}}}\xspace$	$\ensuremath{f_{\mathit{c,max}}}\xspace$	$\frac{\ensuremath{f_{\mathit{c,max}}}\xspace }{\ensuremath{f_{\mathit{c,min}}}\xspace }$	$\ensuremath{{\mathit{NM}}}\xspace$	$\ensuremath{A_{\mathit{inv}}}\xspace$
	[V]	[ps]	[fJ]	[GHz]		[Vdd]
nominal	0.44	47.6	1A.1	3.0	A.5e4	0.36	B.7
a: $\textcolor{red} {N_{ch}\downarrow T\uparrow L\downarrow}$	0.21	34.2	27.2	4.2	7.3e0	0.29	6.1
b: $\textcolor{blue} {N_{ch}\uparrow T\downarrow L\uparrow}$	0.67	B2.6	1B.3	1.5	2.6e9	0.44	34.2
c: $\textcolor{orange}{\ensuremath{t_{\mathit{ox}}}\xspace \downarrow T\uparrow L\downarrow}$	0.23	35.9	1B.8	4.0	7.1e1	0.32	B.9
error						-2.7%	3.6%

¹ k₁=0.67, k₂=2.5, k₃=1 (CMOS with slow PMOST)

The curves in Figs. 3.8-3.11 are the delay time, switching energy, maximum clock frequency, and clock frequency margin   $\ensuremath{{f_{\mathit{c,max}}/f_{\mathit{c,min}}}}\xspace$ for the three cases. From Fig. 3.11 and Table 3.6 it can be seen that the device fails at corner ``a'' because $\ensuremath{{f_{\mathit{c,max}}/f_{\mathit{c,min}}}}\xspace$ is too small for dynamic logic. The noise margins, however, are still 30% $\ensuremath{V_{\mathit{DD}}}\xspace$, which would allow static-logic operation.

Figure 3.8: Inverter delay vs.

Figure 3.9: Switching energy vs.

Figure 3.10: Maximum clock frequency vs.

Figure 3.11: Clock frequency margin $\frac{\ensuremath{f_{\mathit{c,max}}}\xspace }{\ensuremath{f_{\mathit{c,min}}}\xspace }$ vs.

Figure 3.12: Drive current vs.

Figure 3.13: Leakage current vs.

The impact of supply and threshold voltage on maximum clock frequency and switching energy is shown in Figures 3.14 and 3.15. For the simulations $\ensuremath{t_{\mathit{ox}}}\xspace$ was varied from 1nm to 18nm, and $\ensuremath{f_{\mathit{c,max}}}\xspace$ and $\ensuremath{E_{\mathit{s}}}\xspace$ were plotted over $\ensuremath{V_{\mathit{DD}}}\xspace$ and the extracted $\ensuremath{V_{\mathit{T,lin}}}\xspace$. To find an optimum device, one can, e.g., pick a contour in Fig. 3.14 according to the required performance and then, along this contour, find the minimum $\ensuremath{E_{\mathit{s}}}\xspace$ in Fig. 3.15. In comparison, taking the product $\ensuremath{E_{\mathit{s}}}\xspace \ensuremath{t_{\mathit{d}}}\xspace$ as an optimization criterion in Fig. 3.17 would favor devices with a close-to-optimal power efficiency. Most notably, the optimum lies in the range of 0.2...0.4V although these devices were designed for $\ensuremath{V_{\mathit{DD}}}\xspace =\rm1.5V$. Figures 3.18 and 3.19 show the same plots of and for dedicated Ultra-Low-Power devices designed for $\ensuremath{V_{\mathit{DD}}}\xspace =\rm0.2V$ (process A in Section 2.5)

Figure 3.14: Maximum clock frequency vs. and

Figure 3.15: Switching energy vs. and

Figure 3.16: $\ensuremath{f_{\mathit{c,max}}}\xspace /\ensuremath{f_{\mathit{c,min}}}\xspace$ vs. and

Figure 3.17: 1/( ) vs. and

Figure 3.18: Maximum clock frequency vs. and (0.2V ULP technology)

Figure 3.19: Switching energy vs. and (0.2V ULP technology)

This new approach combines the immediate relevance of system models with the accuracy of device simulation at minimum computing effort. Yielding system information directly for arbitrary operating points, like worst-case process corners, makes this method an ideal tool for fast device evaluation without the need of full compact-model characterization during the optimization process.