Bibliography

1

S. Abdollahi-Alibeik, J.P. McVittie, K.C. Saraswat, Ph. Schoenborn, and V. Sukharev.
Analytical Modeling of Silicon Etch Process in High Density Plasma.
J. Vac. Sci. Technol. A, 17(5):2485-2491, 1999.

2

D. Adalsteinsson and J.A. Sethian.
A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography I: Two-Dimensional Simulations.
J. Comput. Phys., 120(1):128-144, 1995.

3

D. Adalsteinsson and J.A. Sethian.
A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography II: Three-Dimensional Simulations.
J. Comput. Phys., 122(2):348-366, 1995.

4

D. Adalsteinsson and J.A. Sethian.
A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography III: Re-Deposition, Re-Emission, Surface Diffusion, and Complex Simulations.
J. Comput. Phys., 138(1):193-223, 1997.

5

A. Anile, W. Allergretto, and C. Ringhofer.
Mathematical Problems in Semiconductor Physics.
2003.

6

J.C. Arnold, D.C. Gray, and H. Sawin.
Influence of Reactant Transport on Fluorine Reactive Ion Etching of Deep Trenches in Silicon.
J. Vac. Sci. Technol. B, 11(6):2071-2080, 1993.

7

Avant! Corporation, TCAD Business Unit, Fremont, CA, USA.
Raphael, Interconnect Analysis Program, Version 2000.2, Reference Manual, 2000.

8

F. Badrieh, H. Puchner, A. Sheikholeslami, C. Heitzinger, and S. Selberherr.
From Feature Scale Simulation to Backend Simulation for a 100nm CMOS Process.
In Proc. 33rd European Solid-State Device Research Conference (ESSDERC), pages 441-444, Estoril, Portugal, 2003. IEEE.

9

D.S. Bang, Z. Krivokapic, M. Hohmeyer, J.P. Mcvittie, and K.C. Saraswat.
Three-Dimensional Simulation for Sputter Deposition Equipment and Process.
In Proc. Simulation of Semiconductor Device and Processes, volume 6, pages 166-169, Springer Wien-New York, 1995.

10

E. Bär and J. Lorenz.
3-D Simulation of LPCVD Using Segment-Based Topography Discretization.
IEEE Trans. Semiconductor Manufacturing, 9(1):67-73, 1996.

11

T.J. Barth and J.A. Sethian.
Numerical Schemes for the Hamilton-Jacobi and Level Set Equations on Triangulated Domains.
J. Comput. Phys., 145(1):1-40, 1998.

12

F.S. Becker, D. Pawlik, H. Schafer, and G. Staudigl.
Process and Film Characterization of Low Pressure Tetraethylorthosilicate-Borophosphosilicate Glass.
J. Vac. Sci. Technol. B, 4(3):732-744, 1986.

13

F. H. Bell and O. Joubert.
Polysilicon Gate Etching In High Density Plasmas. V. Comparison Between Quantitative Chemical Analysis Of Photoresist And Oxide Masked Polysilicon Gates Etched In Hbr/Cl$_{2}$/O$_{2}$ Plasmas.
J. Vac. Sci. Technol. B, 14:3473, 1996.

14

T. Binder.
Rigorous Integration of Semiconductor Process and Device Simulators.
Dissertation, Technische Universität Wien, 2002.
http://www.iue.tuwien.ac.at/phd/binder.

15

T. Binder, K. Dragosits, T. Grasser, R. Klima, M. Knaipp, H. Kosina, R. Mlekus, V. Palankovski, M. Rottinger, G. Schrom, S. Selberherr, and M. Stockinger.
MINIMOS-NT User's Guide.
Institut für Mikroelektronik, 1998.

16

C. Bulucea and R. Rossen.
Trench DMOS Transistor Technology for High Current (100A Range) Switching.
Solid-State Electron., 34(5):493-507, 1991.

17

T.S. Cale, M.O. Bloomfield, D.F. Richards, K.E. Jansen, and M.K. Gobbert.
Integrated Multiscale Process Simulation.
Computational Materials Science, 23(1-4):3-14, 2002.

18

T.S. Cale, T.P. Merchant, L.J. Borucki, and A.H. Labun.
Topography Simulation for the Virtual Wafer Fab.
Thin Solid Films, 365(2):152-175, 2000.

19

T.S. Cale and G.B. Raupp.
A Unified Line-of-Sight Model of Deposition in Rectangular Trenches.
J. Vac. Sci. Technol. B, 8(6):1242-1248, 1990.

20

J.P. Chang, J.C. Arnold, G.C.H. Zau, and H.S. Shin.
Kinetic Study of Low Energy Argon Ion-Enhanced Plasma Etching of Polysilicon with Atomic/Molecular Chlorine.
J. Vac. Sci. Technol. A, 15(4):1853-1863, 1997.

21

J.P. Chang, Y.S. lin, and K. Chu.
Rapid Thermal Chemical Vapor Deposition of Zirconium Oxide for Metal-Oxide-Semiconductor Field Effect Transsitor Applications.
J. Vac. Sci. Technol. B, 19(5):1782-1787, 2001.

22

J.P. Chang, A.P. Mahorowala, and H.H. Sawin.
Plasma-Surface Kinetics and Feature Profile Evolution in Chlorine Etching of Polysilicon.
J. Vac. Sci. Technol. A, 16(1):217-224, 1998.

23

J.P. Chang and H.H. Sawin.
Kinetic Study of Low Energy Ion-Enhanced Polysilicon Etching Using Cl, Cl$_{2}$, and Cl$^{+}$ Beam Scattering.
J. Vac. Sci. Technol. A, 15(3):610-615, 1997.

24

E.S. Choi and H.H. Lee.
Energetics of Copper Deposition Based on cu(i) Precursors.
J. Electrochem. Soc., 147(10):3730-3733, 2000.

25

J. W. Coburn and H. F. Winters.
Conductance Considerations in the Reactive Ion Etching of High Aspect Ratio Features.
Appl. Phys. Lett., 55:2730-2732, 1989.

26

M.E. Coltrin, R.J. Kee, and F.M. Rupley.
Surface Chmekin (Version 4.0): A Fortran Package for Analyzing Heterogeneous Chemical Kinetics at a Solid-State-Gas-Phase Interface.
Technical report, Sandia National Laboratories, 1991.

27

K. Dharmawardana and G. Amaratunga.
Analytical Model for High Current Density Trench Gate MOSFET.
In Proc. of the 10th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pages 351-354, Kyoto, Japan, 1998.

28

K. Dharmawardana and G. Amaratunga.
Modeling of High Current Density Trench Gate MOSFET.
IEEE Trans. Electron Devices, 47(12):2420-2428, 2000.

29

F.H. Dill, A.R. Neureuther, J.A. Tuttle, and E.J. Walker.
Modeling Projection Printing of Positive Photoresist.
IEEE Trans. Electron Devices, 22(7):456-464, 1975.

30

M.K. Gobbert, T.P. Merchant, L. J. Borucki, and T.S. Cale.
A Multiscale Simulator for Low Pressure Chemical Vapor Deposition.
J. Electrochem. Soc., 144:3945, 1997.

31

R.A. Gottscho.
Ion Transport Anisotropy in Low Pressure, High Density Plasmas.
J. Vac. Sci. Technol. B, 11(5):1884-1889, 1993.

32

R.A. Gottscho, C.W. Jurgensen, and D.J. Vitkavage.
Microscopic Uniformity in Plasma Etching.
J. Vac. Sci. Technol. B, 10(5):2133-2147, 1992.

33

C. Großmann and H.G. Roos.
Numerics of Partial Differential Equations.
B.G. Teubner, Stuttgart, 1994.

34

K. Harafuji, M. Ohkuni, M. Kubota, H. Nakagawa, and A. Misaka.
Simulation Approach for Achieving Configuration Independent Poly-Silicon Gate Etching.
In Technical Digest 1995 International Electron Devices Meeting (IEDM), pages 105-108, New York, 1995. IEEE.

35

C. Heitzinger.
Simulation and Inverse Modeling of Semiconductor Manufacturing Processes.
Dissertation, Technische Universität Wien, 2002.
http://www.iue.tuwien.ac.at/phd/heitzinger.

36

C. Heitzinger, J. Fugger, O. Häberlen, and S. Selberherr.
On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method.
In Proc. 32th European Solid-State Device Research Conference (ESSDERC), pages 347-350, Florence, Italy, 2002. University of Bologna.

37

C. Heitzinger, J. Fugger, O. Häberlen, and S. Selberherr.
Simulation and Inverse Modeling of TEOS Deposition Processes Using a Fast Level Set Method.
In Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pages 191-194, Kobe, Japan, 2002. Business Center for Academic Societies, Japan.

38

C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, and S. Selberherr.
Feature Scale Simulation of Advanced Etching Processes.
In Proc. 204th Meeting of the Electrochemical Society (ECS), page 1259, Orlando,USA, 2003.

39

C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, and S. Selberherr.
Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminium/TEOS Process.
IEEE Trans. Electron Devices, 51(7):1129-1134, 2004.

40

C. Heitzinger, A. Sheikholeslami, J. Fugger, O. Häberlen, M. Leicht, and S. Selberherr.
A Case Study in Predictive Three-Dimensional Topography Simulation Based on a Level-Set Algortihm.
In Proc. 205th Meeting of the Electrochemical Society (ECS), pages 132-142, San Antonio, USA, 2004.

41

C. Heitzinger, A. Sheikholeslami, J.M. Park, and S. Selberherr.
A Method for Generating Structurally Aligned Grids and its Application to the Simulation of a Trench Gate MOSFET.
In Proc. 33rd European Solid-State Device Research Conference (ESSDERC), pages 457-460, Estoril, Portugal, 2003.

42

C. Heitzinger, A. Sheikholeslami, J.M. Park, and S. Selberherr.
A Method for Generating Structurally Aligned Grids for Semiconductor Device Simulation.
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 24(10):1485-1491, 2005.

43

C. Heitzinger, A. Sheikholeslami, H. Puchner, and S. Selberherr.
Predictive Simulation of Void Formation During the Deposition of Silicon Nitride and Silicon Dioxide Films.
In Proc. 203rd Meeting of the Electrochemical Society (ECS), pages 356-365, Paris, France, 2003.

44

C. Heitzinger, A. Sheikholeslami, and S. Selberherr.
Preditive Simulation of Etching and Deposition Processes Using the Level Set Method.
In Proc. International Workshop on Challenges in Predictive Process Simulation (ChiPPS), pages 65-66, Prag, Czech Republic, 2002.

45

C. Hollauer.
Implementierung einer HDF5-Datenschnittstelle für den Wafer-State Server.
Diplomarbeit, Technische Universität Wien, 2002.

46

S. Holzer, A. Sheikholelsami, S. Wagner, C. Heitzinger, T. Grasser, and S. Selberherr.
Optimization and Inverse Modeling for TCAD Applications.
In Symposium on Nano Device Technology, pages 113-116, Hsinchu,Taiwan, 2004.

47

A.D. Bailey III, M.C.M. Van de Sanden, J.A. Gregus, and R.A. Gottscho.
Scaling of Si and GaAs Trench Etch Rates with Aspect Ratio, Feature Width, and Substrate Temperature.
J. Vac. Sci. Technol. B, 13(1):92-104, 1995.

48

M.M. Islamraja, C. Chang, J.P. Mcvittie, M.A. Cappelli, and K.C. Saraswat.
Two Precursor Model for Low-Pressure Chemical Vapor Deposition of Silicon Dioxide from Tetraethylorthosilicate.
J. Vac. Sci. Technol. B, 11(3):720-726, 1993.

49

R.J. Kee, F.M. Rupley, and J.A. Miller.
CHEMKIN II: A Fortran Chemical Kinetics Package for the Analysis of Gas Phase Chemical Kinetics.
Technical report, Sandia National Laboratories, 1989.

50

R.J. Kee, F.M. Rupley, J.A. Miller, M.E. Coltrin, J.F. Grcar, E. Meeks, H.K. Moffat, A.E. Lutz, G. Dixon-Lewis, M.D. Smooke, J. Warnatz, G.H. Evans, R.S. Larson, R.E. Mitchell, L.R. Petzold, W.C. Reynolds, M. Caracotsios, W.E. Stewart, P. Glarborg, C. Wang, O. Adigun, W.G. Houf, C.P. Chou, and S.F. Miller.
Chemkin Collection, Release 3.7.1.
Technical report, Reaction Design, Inc., San Diego, CA, 2003.

51

R. Klima.
Three-Dimensional Device Simulation with MINIMOS-NT.
Dissertation, Technische Universität Wien, 2002.
http://www.iue.tuwien.ac.at/phd/klima.

52

J. Krause and W. Fichtner.
Boundary Sensitive Mesh Generation Using an Offsetting Technique.
In Proc. 2nd Symposium on Trends in Unstructured Mesh Generation (5th US Congress on Computational Mechanics), Boulder, CO, USA, 1999.

53

U.H. Kwon and W.J. Lee.
Three-Dimensional Deposition Topography Simulation Based on New Combination of Flux Distribution and Surface Representaion Algorithms.
Thin Solid Films, 445:80-89, 2003.

54

J. Lorenz, B. Baccus, and W. Henke.
Three-Dimensional Process Simulation.
Microelectronic Engineering, 34(1):85-100, 1996.

55

G. Lu, M. Bora, L.L. Tedder, and G.W. Rubloff.
Integrated Dynamic Simulation of rapid Thermal Chemical Vapor Deposition of Polysilicon.
IEEE Trans. Semiconductor Manufacturing, 11(1):63-74, 1998.

56

l.Y. Cheng, J.P. Mcvittie, and K.C. Saraswat.
New Structure to Identify Step Coverage Mechanisms in Chemical Vapor Deposition of Silicon Dioxide.
Appl. Phys. Lett., 58(19):2147-2149, 1991.

57

P. Markowich.
The Stationary Semiconductor Device Equations.
Springer, Wien-New York, 1986.

58

P.A. Markowich, C.A. Ringhofer, and C. Schmeiser.
Semiconductor Equations.
Springer, Wien-New York, 1990.

59

R. Martinez.
On the Design of Very Low Power Integrated Circuits.
Dissertation, Technische Universität Wien, 1999.
http://www.iue.tuwien.ac.at/phd/martinez.

60

A. Mikasa and K. Harafuji.
Simulation Study of Micro-Loading Phenomena in Silicon Dioxide Hole Etching.
IEEE Trans. Electron Devices, 44(5):751-760, 1997.

61

V. Moroz, S. Motzny, and K. Lilja.
A Boundary Conforming Mesh Generation Algorithm for Simulation of Devices with Complex Geometry.
In Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pages 293-295, Boston, MA, USA, 1997.

62

A.R. Neureuther.
Simulation of Semiconductor Lithography and Topography.
Technical report, Department of Electrical Engineering and Computer Science, University of California, Berkeley, 1995.

63

S. Osher and J.A. Sethian.
Fronts Propagating with Curvature Dependent Speed: Algorithm Based on Hamilton-Jacobi Formulation.
J. Comput. Phys., 28:907-922, 1991.

64

W. Pyka.
Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing.
Dissertation, Technische Universität Wien, 2000.
http://www.iue.tuwien.ac.at/phd/pyka.

65

W. Pyka, C. Heitzinger, N. Tamaoki, T. Takase, T. Ohmine, and S. Selberherr.
Monitoring Arsenic In-Situ Doping with Advanced Models for Poly-Silicon CVD.
In Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pages 124-127, Athens, Greece, 2001. Springer, Wien-New York.

66

W. Pyka, R. Martins, and S. Selberherr.
Efficient Algorithms for Three-Dimensional Etching and Deposition Simulation.
In Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pages 69-72, Leuven, Belgium, 1998.

67

G.B. Raupp, F.A. Shemansky, and T.S. Cale.
Kinetics and Mechanism of Silicon Dioxide Deposition Through Thermal Pyrolysis of Tetraethoxysilane.
J. Vac. Sci. Technol. B, 10(6):2422-2430, 1992.

68

E. Rouy and A. Tourin.
A Viscousity Solution Approach to Shape-from-Shading.
SIAM J. Numer. Anal., 29(3):867-884, 1992.

69

O. Runborg.
Finite Difference Methods for the Advection Equation.
2D1250, Tillämpade Numeriska Methoder II, pages 1-6, 2003.

70

J. Ruppert.
A Delaunay Refinement Algorithm for Quality 2-Dimensional Mesh Generation.
Journal of Algorithms, 18(3):548-585, 1995.

71

G. Russo and P. Smereka.
A Level Set Method for the Evolution of Faceted Crystals.
SIAM J. Sci. Comput., 21(6):2073-2095, 2000.

72

E. Scheckler.
Algorithms for Three-Dimensional Simulation of Etching and Deposition Processes in Integrated Circuit Fabrication.
PhD thesis, University of California, Berkeley, CA, USA, 1991.

73

E.W. Scheckler and A.R. Neureuther.
Models and Algorithms for Three-Dimensional Topography Simulation with SAMPLE-3D.
IEEE Trans. Computer-Aided Design, 13(2):219-230, 1994.

74

G. Schumicki and P. Seegebrecht.
Prozeßtechnologie.
Springer, 1991.

75

S. Selberherr.
Analysis and Simulation of Semiconductor Devices.
Springer, Wien, New York, 1984.

76

J.A. Sethian.
Curvature and the Evolution of Fronts.
Commun. in Math. Physics, 101:487-499, 1985.

77

J.A. Sethian.
Curvature Flow and Entropy Conditions Applied to Grid Generation.
J. Comput. Phys., 115(2):440-454, 1994.

78

J.A. Sethian.
A Fast Marching Level Set Method for Monotonically Advancing Fronts.
In Proc. Nat. Acad. Sci., 1996.

79

J.A. Sethian.
A Review of the Theory, Algorithms, and Applications of Level Set Methods for Propagating Interfaces.
Acta Numerica, Cambridge University Press, Cambridge, 1996.

80

J.A. Sethian.
Level Set Methods and Fast Marching Methods.
Cambridge University Press, Cambridge, 1999.

81

A. Sheikholeslami, E. Al-Ani, R. Heinzl, C. Heitzinger, F. Parhami, F. Badrieh, H. Puchner, T. Grasser, and S. Selberherr.
Level Set Method Based General Topography Simulator and its Application in Interconnect processes.
In Proc. International Conference on Ultimate Integration of Silicon (ULIS), pages 139-142, Bologna, Italy, 2005.

82

A. Sheikholeslami, C. Heitzinger F. Badrieh, H. Puchner, and S. Selberherr.
Three-Dimensional Topography Simulation Based on a Level Set Method.
In Proc. 27th IEEE International Spring Seminar on Electronics (ISSE),Vol. 2, pages 263-265, Sofia, Bulgaria, 2004.

83

A. Sheikholeslami, C. Heitzinger, E. Alani, R. Heinzl, T. Grasser, and S. Selberherr.
Three-Dimensional Surface Evolution Using a Level Set Method.
In Iranian Ph.D. Students Seminar on Computer Science, Mathematics and Statistics (ICSMS), Paris, France, 2004.

84

A. Sheikholeslami, C. Heitzinger, T. Grasser, and S. Selberherr.
Three-Dimensional Topography Simulation for Deposition and Etching Processes Using a Level Set Method.
In Proc. 24th International Conference on Microelectronics (MIEL), pages 241-244, Nis, Serbia and Montenegro, 2004.

85

A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, and S. Selberherr.
Simulation of Void Formation in Interconnect Lines.
In SPIE's first International Symposium on Microtechnologies for the New Millennium: VLSI Circuits and Systems, pages 445-452, Gran Canaria, Spain, 2003.

86

A. Sheikholeslami, C. Heitzinger, and S. Selberherr.
A Method for Generating Structurally Aligned Grids Using a Level Set Approach.
In Proc. 17th European Simulation Multiconference (ESM): Modeling and Simulation, pages 496-501, Nottingham, England, 2003.

87

A. Sheikholeslami, C. Heitzinger, S. Selberherr, F. Badrieh, and H. Puchner.
Capacitances in the Backend of a 100nm CMOS Process and their Predictive Simulation.
In Beiträge der Informationstagung Mikroelectronik (ME), pages 481-486, Wien, Österreich, 2003.

88

A. Sheikholeslami, S. Holzer, C. Heitzinger, M. Leicht, O. Häberlen, J. Fugger, T. Grasser, and S. Selberherr.
Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process.
In Proc. PhD Research in Microelctronics and Electronics (PRIME), Vol. 2, pages 279-282, Lausanne, Switzerland, 2005.

89

A. Sheikholeslami, F. Parhami, R. Heinzl, E. Al-Ani, C. Heitzinger, F. Badrieh, H. Puchner, T. Grasser, and S. Selberherr.
Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines.
In Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pages 187-190, Tokyo, Japan, 2005.

90

K. Shenai.
Optimized Trench MOSFET Technologies for Power Devices.
IEEE Trans. Electron Devices, 39(6):1435-1443, 1992.

91

J.R. Shewchuk.
Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator.
In Proc. First Workshop on Applied Computational Geometry, pages 124-133, Philadelphia, PA, USA, 1996.

92

J.R. Shewchuk.
Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator.
In M.C. Lin and D. Manocha, editors, Applied Computational Geometry: Towards Geometric Engineering, volume 1148 of Lecture Notes in Computer Science, pages 203-222. Springer, Berlin, 1996.
From the First ACM Workshop on Applied Computational Geometry.

93

V.K. Singh, E.S.G. Shaqfeh, and J.P. Mcvittie.
Simulation of Profile Evolution in Silicon Reactive Ion Etching with Re-Emission and Surface Diffusion.
J. Vac. Sci. Technol. B, 10(3):1091-1104, 1992.

94

D.L. Smith, B. Wacker, S.E. Ready, C.C. Chen, and A.S. Alimonda.
Mechanism of SiN$_x$H$_y$ Deposition from NH$_3$-SiH$_4$ Plasma.
J. Electrochem. Soc., 137:614-623, 1990.

95

D. Sylvester, J.C. Chen, and C. Hu.
Investigation of Interconnect Capacitance Characterization Using Charge-Based Caapcitance Measurment (CBCM) Technique and Three-Dimensional Simulation.
IEEE J. Solid-State Circuits, 33(3), 1998.

96

J.F. Thompson, Z.U.A. Warsi, and C.W. Mastin.
Numerical Grid Generation.
North Holland, Amsterdam, 1985.

97

K. Toh.
Algorithms for Three-Dimensional Simulation of Photoresist Development.
PhD thesis, University of California, Berkeley, CA, USA, 1990.

98

K.K.H. Toh, A.R. Neureuther, and E.W. Scheckler.
Algorithms for Simulation of Three-Dimensional Etching.
IEEE Trans. Computer-Aided Design, 13(5):616-624, 1994.

99

M. Tuda, K. Ono, and K. Nishikawa.
Effects of Etch Products and Surface Oxidation on Profile Evolution During Electron Cyclotron Resonance Plasma Etching of Poly-Si.
J. Vac. Sci. Technol. B, 14(5):3291-3298, 1996.

100

M. Tuda, K. Shintani, and H. Ootera.
Profile Evolution During Polysilicon Gate Etching with Low-Pressure High-Density Cl$_{2}$/HBr/O$_{2}$ Plasma Chemistries.
J. Vac. Sci. Technol. A, 19(3):711-717, 2001.

101

D. Ueda, H. Takagi, and G. Kano.
A New Vertical Power MOSFET Structure with Extremely Low On Resistance.
IEEE Trans. Electron Devices, ED-32(1):2-6, January 1985.

102

D. Wake, K. Lilja, and V. Moroz.
A Hybrid Mesh Generation Method for Two and Three Dimensional Simulation of Semiconductor Processes and Devices.
In Proc. 7th International Meshing Roundtable, pages 159-166, Dearborn, MI, USA, 1998.

103

S. Yamamoto, T. Kure, M. Ohgo, T. Matsuzama, S. Tachi, and H. Sunami.
A Two-Dimensional Etching Profile Simulator: ESPRIT.
IEEE Trans. Computer-Aided Design, 6(3):417-422, 1987.

104

H.K. Zhao, T. Chan, B. Merriman, and S. Osher.
A Variational Level Set Approach to Multiphase Motion.
J. Comput. Phys., 127(1):179-195, 1996.