Own Publications

1

A. Sheikholeslami, F. Parhami, H. Puchner, and S. Selberherr.
Planarization of Passivation Layers during Manufacturing Processes of Image Sensors.
Journal of Optical and Quantum Electronics. (Submitted for publication).

2

A. Sheikholeslami, F. Parhami, H. Puchner, and S. Selberherr.
Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers.
Journal of Physics. (Submitted for publication).

3

S. Holzer, M. Wagner, A. Sheikholeslami, M. Karner, G. Span, T. Grasser, and S. Selberherr.
An Extendable Multi-Purpose Simulation and Optimization Framework for Thermal Problems in TCAD Applications.
In Proc. Thermal Investigations of ICs and Systems (THERMINIC), Nice, Côte d'Azur, France, 2006. (In print).

4

A. Sheikholeslami, F. Parhami, H. Puchner, and S. Selberherr.
Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers.
In Proc. International Conference on Nanoscience and Technology (ICNT), pages 163-164, Basel, Switzerland, 2006.

5

S. Holzer, A. Sheikholeslami, M. Karner, and T. Grasser.
Comparison of Deposition Models for TEOS CVD Process.
In Workshop on Dielectrics in Microelectronics (WODIM), pages 158-159, Catania, Italy, 2006.

6

A. Sheikholeslami, C. Heitzinger, S. Holzer, R. Heinzl, M. Spevak, M. Leicht, O. Häberlen, J. Fugger, F. Badrieh, F. Parhami, H. Puchner, T. Grasser, and S. Selberherr.
Applications of Two- and Three-Dimensional General Topography Simulator in Semiconductor Manufacturing Processes.
In Proc. of 14th Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, 2006.

7

C. Heitzinger, A. Sheikholeslami, J.M. Park, and S. Selberherr.
A Method for Generating Structurally Aligned Grids for Semiconductor Device Simulation.
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 24(10):1485-1491, 2005.

8

A. Sheikholeslami, F. Parhami, R. Heinzl, E. Al-Ani, C. Heitzinger, F. Badrieh, H. Puchner, T. Grasser, and S. Selberherr.
Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines.
In Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pages 187-190, Tokyo, Japan, 2005.

9

A. Sheikholeslami, S. Holzer, C. Heitzinger, M. Leicht, O. Häberlen, J. Fugger, T. Grasser, and S. Selberherr.
Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process.
In Proc. PhD Research in Microelctronics and Electronics (PRIME), Vol. 2, pages 279-282, Lausanne, Switzerland, 2005.

10

A. Sheikholeslami, E. Al-Ani, R. Heinzl, C. Heitzinger, F. Parhami, F. Badrieh, H. Puchner, T. Grasser, and S. Selberherr.
Level Set Method Based General Topography Simulator and its Application in Interconnect Processes.
In Proc. International Conference on Ultimate Integration of Silicon (ULIS 2005), pages 139-142, Bologna, Italy, 2005.

11

A. Sheikholeslami, C. Heitzinger, E. Alani, R. Heinzl, T. Grasser, and S. Selberherr.
Three-Dimensional Surface Evolution Using a Level Set Method.
In Iranian Ph.D. Students Seminar on Computer Science, Mathematics and Statistics (ICSMS), Paris, France, 2004.

12

C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, and S. Selberherr.
Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminium/TEOS Process.
IEEE Trans. Electron Devices, 51(7):1129-1134, 2004.

13

A. Sheikholeslami, C. Heitzinger, T. Grasser, and S. Selberherr.
Three-Dimensional Topography Simulation for Deposition and Etching Processes Using a Level Set Method.
In Proc. 24th International Conference on Microelectronics (MIEL), pages 241-244, Nis, Serbia and Montenegro, 2004.

14

A. Sheikholeslami, C. Heitzinger, F. Badrieh, H. Puchner, and S. Selberherr.
Three-Dimensional Topography Simulation Based on a Level Set Method.
In Proc. 27th IEEE International Spring Seminar on Electronics (ISSE),Vol. 2, pages 263-265, Sofia, Bulgaria, 2004.

15

C. Heitzinger, A. Sheikholeslami, J. Fugger, O. Häberlen, M. Leicht, and S. Selberherr.
A Case Study in Predictive Three-Dimensional Topography Simulation Based on a Level-Set Algortihm.
In Proc. 205th Meeting of the Electrochemical Society (ECS), pages 132-142, San Antonio, USA, 2004.

16

S. Holzer, A. Sheikholelsami, S. Wagner, C. Heitzinger, T. Grasser, and S. Selberherr.
Optimization and Inverse Modeling for TCAD Applications.
In Symposium on Nano Device Technology, pages 113-116, Hsinchu, Taiwan, 2004.

17

A. Sheikholeslami, C. Heitzinger, S. Selberherr, F. Badrieh, and H. Puchner.
Capacitances in the Backend of a 100nm CMOS Process and their Predictive Simulation.
In Beiträge der Informationstagung Mikroelektronik (ME), pages 481-486, Wien, Austria, 2003.

18

A. Sheikholeslami, C. Heitzinger, and S. Selberherr.
A Method for Generating Structurally Aligned Grids Using a Level Set Approach.
In Proc. 17th European Simulation Multiconference (ESM): Modeling and Simulation, pages 496-501, Nottingham, England, 2003.

19

A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, and S. Selberherr.
Simulation of Void Formation in Interconnect Lines.
In SPIE's first International Symposium on Microtechnologies for the New Millennium: VLSI Circuits and Systems, pages 445-452, Gran Canaria, Spain, 2003.

20

C. Heitzinger, A. Sheikholeslami, H. Puchner, and S. Selberherr.
Predictive Simulation of Void Formation During the Deposition of Silicon Nitride and Silicon Dioxide Films.
In Proc. 203rd Meeting of the Electrochemical Society (ECS), pages 356-365, Paris, France, 2003.

21

F. Badrieh, H. Puchner, A. Sheikholeslami, C. Heitzinger, and S. Selberherr.
From Feature Scale Simulation to Backend Simulation for a 100nm CMOS Process.
In José Franca and Paulo Freitas, editors, Proc. 33rd European Solid-State Device Research Conference (ESSDERC), pages 441-444, Estoril, Portugal, 2003.

22

C. Heitzinger, A. Sheikholeslami, J.M. Park, and S. Selberherr.
A Method for Generating Structurally Aligned Grids and its Application to the Simulation of a Trench Gate MOSFET.
In Proc. 33rd European Solid-State Device Research Conference (ESSDERC), pages 457-460, Estoril, Portugal, 2003.

23

C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, and S. Selberherr.
Feature Scale Simulation of Advanced Etching Processes.
In Proc. 204th Meeting of the Electrochemical Society (ECS), page 1259, Orlando, USA, 2003.

24

C. Heitzinger, A. Sheikholeslami, and S. Selberherr.
Preditive Simulation of Etching and Deposition Processes Using the Level Set Method.
In Proc. International Workshop on Challenges in Predictive Process Simulation (ChiPPS), pages 65-66, Prag, Czech Republic, 2002.