Device miniaturization has steadily progressed since the invention of the integrated circuit in the 1950s. The many challenges which arose along the years were surpassed by advancements in processing technologies. Smaller devices meant more chips per wafer, lower power consumption, and higher speeds. Eventually, it is expected that device miniaturization will reach a limit and the basics elements of the current device technology have shown signs of weariness.

Naturally, several ideas have appeared with claims to overcome the challenges. Some involve the reformulation of a device or a process, while others involve enhancements of the current technology. Depending on the chosen path, the cost of implementation can be a drawback for the fast implementation of the technology by industry. It is not uncommon that a new semiconductor plant requires investments in the excess of two billion US dollars. It is unlikely that any industry would be willing to invest, in the short and middle term, in the development of technologies not compatible with their current plant. Therefore, a solution for the current integration problems should take into consideration the processing technologies available in the industry today.

Three-dimensional integration is a well balanced solution. It presents possibilities for an increase in device integration in every sense: device miniaturization, lower power consumption, and higher speeds. There are varying approaches for the manufacture of devices, but the majority relies on a “through silicon via” (TSV) to electrically bind the devices along the third dimension. The construction of a TSV is challenging, mainly due to its size. Among the required processing steps are the etching of high aspect ratio structures, wafer thinning, and several film depositions. A particular problem with TSVs is the mechanical stability of the structure and its influence on its surroundings. Such a large metal structure in the middle of the silicon circuit is prone to create a high level of stress during device operation and processing.

Within this work an extensive analysis of the mechanical aspects of the TSV is performed by means of simulations. A macro scale investigation of the mechanical effects of the TSV on its surroundings is performed. Subsequently, the via is analyzed locally, with a consideration of processing and handling scenarios. Lastly, microstructural effects are studied for the formation of residual stress during metal growth. The main objective is to provide a comprehensive characterization of the mechanical stability of the TSV, from its effects on the silicon circuit down to the manufacturing of the via. A collection of simulation techniques and models is developed and presented as the main contribution of this work.