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2.2 Device Design Techniques

Various design techniques are available to optimize the device behavior and to integrate high-voltage devices in integrated circuits. In the following considerations the two important properties blocking voltage and on-current are of special interest. Closely related is the on-resistance which also determines the power losses in the device. To achieve a cost efficient design the required chip surface is one of the most important constraints which has to be minimized. Other important goals not considered here are, for example, the turn on and off delays which lead to the maximum switching frequency.

2.2.1 Vertical and Lateral Devices

In the previous section, the basics of the two device types MOSFET and IGBT for high-voltage and high power applications were explained. In the corresponding figures, the devices were shown in vertical orientation which is typically used for discrete power devices. Here, the main current flow is oriented vertically, meaning perpendicular to the semiconductor surface. The drain/collector contacts are placed at the bottom of the devices. The elementary transistor cells can be placed side by side on the chip and can be simply connected in parallel. This is a common method to achieve a high current component and is especially used for discrete high current power devices.

Especially in smart power devices, the processing and packaging often requires that all contacts must be situated on the top side of the die. There are techniques that allow the use of vertical structures in planar environments. The vertical current is commonly collected by a highly doped buried layer. These collected carriers are transported to the top surface using sinker structures. This concept typically looks similar to the structure shown in Fig. 2.4. To keep the resistivity low, the buried layer and sinker structures have to be highly doped. These types of devices are also called horizontal devices [6].

Figure 2.4: Vertical DMOS structure with its drain contact on top of the device. The transport of the carriers to the surface is accomplished by a highly n-doped buried layer and sinker structure.

In contrast to the vertical devices, the dominant current flow of lateral devices is in horizontal direction, that is, in parallel to the semiconductor surface [31]. For low-voltage and low-power transistors like in CMOS environments, this is the typical design method for MOSFET devices (see Fig. 2.5).

Figure 2.5: Typical CMOS structure with lightly doped drain and source extensions (LDD) on a p-type substrate or on a p-type epitaxial grown layer.

For devices having higher blocking voltages, long drift regions are required, which are necessary to keep the electric field moderate in blocking state. The typically used MOS transistor in lateral high-voltage designs is the LDMOS (Lateral Double-diffused MOSFET) [32]. The basic scheme of an LDMOS transistors is shown in Fig. 2.6.

Figure 2.6: Basic lateral high voltage double diffused MOS transistor (LDMOS). The electric field is consumed by the relatively low doped drift region.

However, in the shown version of the device, high voltages in the junction area between channel and drift zone will lead to low breakdown voltages (see Fig. 2.7(b)). The field in the junction can be reduced by incorporating a very low doping in the drift region [32]. Since this increases the resistance other solutions are required. A better method to decrease the peak of the electric field is the RESURF technique which is discussed in the next section [33].

Comparing the vertical and the lateral design in terms of integrability into the CMOS processes, as it is required in smart power devices, clearly favors the LDMOS [34]. Here, the voltage rating for each individual transistor is achieved by changing implantation conditions and by adjusting the device layout. It is also simpler to implement field shaping techniques in lateral than in vertical design. Hence, lateral devices are traditionally better optimized for high-voltage applications, while vertical devices are mainly used for high-current applications [35]. Optimizations also make the chip surface of lateral LDMOS devices smaller compared to vertical implementations [36].

On the other hand, the fabrication of buried layers and sinkers which redirect the current to the silicon surface considerably increase the complexity of the standard CMOS process for vertical devices [34]. Additionally, drain contacts are often tied together in vertical design. This complicates the monolithic integration of n- and p-channel devices, because independent buried layers are required. However, an important advantage of the vertical DMOS is the increased electrical safe operating area, which is of special importance for electrostatic discharge (ESD) [37,34].

2.2.2 Reduced Surface Field Technique

To resist high blocking voltages, the simplest approach is to make long and lowly doped drift regions. Both parameters, length and low doping, lead to large on-resistance ( $ \mathrm{R}_{\mathrm{DS,on}}$ ) and therefore to higher drop voltages, and higher power loss. Another aspect of long, lateral drift regions is the additionally required chip area which increases costs. A trade off between blocking voltage and on-resistance has to be found. For a given breakdown voltage the optimal drift length and doping can be determined [38,39].

The peak electric field is typically concentrated near the pn-junction close to the surface which is illustrated by a diode in Fig. 2.7(a).

Figure 2.7: The blocking voltage drop in the classical diode structure (a) is only in the space charge region around the pn-junction as indicated by the dotted line. The electric field along the surface of the device is schematically shown. The thinner drift-zone which is used in the RESURF structure (b) causes the space charge region to extend up to the silicon surface in the blocking state. The voltage drop is therefore distributed along the drift zone which leads to a reduced peak field.
(a) Classical Diode Structure

(b) RESURF Diode Structure

With the RESURF (REduced SURface Field) concept introduced by Appels and Vaes this maximum field can be reduced [33,40]. This is accomplished by changing the design such that the space charge region in the blocking state extends over the whole drift zone. The resulting charge distribution leads to a continuous potential drop along the whole drift zone and not only across the junctions. Therefore the same terminal voltages cause lower electric fields in the device. This effect is illustrated in Fig. 2.7(b) by a diode structure, too. RESURF is used in modern LDMOS devices. In n-channel LDMOS devices commonly a p-doped layer is introduced below the drift region and the thickness of the drift region is chosen that in blocking mode the space charge region extends up to the silicon surface, just like in the diode structure. Fig. 2.8 shows an implementation using a p-type epitaxial layer. For a given maximum blocking voltage the length of the drift region can therefore be reduced. This minimizes both critical parameters, the on-resistance and the chip surface.

Figure 2.8: High-voltage LDMOS transistor using the RESURF (reduced surface field) technique and a field plate deposited on top of the LOCOS (LOCal Oxidation of Silicon). Both methods reduce the peak electric field near the surface.

Since the peak fields are avoided by using the RESURF technique, the doping of the drift region can be increased and the drift zone can be shorted. Both variations reduce the on-resistance of the MOSFET. Therefore the drop voltage and the power dissipation are considerably lower. The RESURF concept is nowadays widely used in high-voltage LDMOSFET structures [41,42,43].

An extension of the RESURF concept is the Super Junction structure which basically consists of layers or stripes of alternating n- and p-doped areas (see Fig. 2.9) [44].

Figure 2.9: The basic structure of a Super Junction diode. In the blocking state the space charge region extends over the whole stacked p- and n-type layers. This allows high doping levels which give a low on-resistance with high blocking capability.

With reverse bias, the space charge region extends throughout the whole drift area and removes all free carriers. Electric field peaks are avoided which allows high blocking voltages. Also a high doping can be chosen for the stripes, which results in a very low on-resistance. Production of such Super Junction structures is quite complex and was realized, for example, in the vertical COOLMOS $ ^\mathrm{TM}$ [45] structure by Infineon Technologies.

next up previous contents
Next: 2.3 Smart Power Devices Up: 2. High-Voltage and Power Previous: 2.1 High-Voltage Device Types

O. Triebl: Reliability Issues in High-Voltage Semiconductor Devices