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2.1 High-k Gate Stacks

Moore [18] predicted the number of transistors to double on a chip every two years. To be able to keep that exponential growth the components on the chip have to shrink accordingly every chip generation. However, it is not sufficient to reduce only the gate length and width. It also involves a reduction of all other dimensions including the gate/source and gate/drain alignment, the oxide thickness, and the depletion layer widths. Scaling of the depletion layer width also demands a corresponding adjustment of the substrate doping concentration [19].

At the $ 45$nm node the so called geometric scaling or classic scaling is strongly impeded. For instance, the gate oxide thickness in 2009 was $ 7.5\,$Å according to the ITRS[20]. At this thickness the scaling of about $ \sim0.7$ per generation is hindered due to the few atom layers of $ SiO_{2}$ left and the gate leakage caused by tunneling. So instead of scaling the oxide thickness down, the material has to be exchanged. Therefore, the oxide thickness is exchanged by the EOT with respect to $ SiO_{2}$. The material is actually thicker than silicon dioxide requires, but exhibits at the same time a much higher k-value. Thus, the gate leakage can be surpressed, while maintaining control over the channel.

The switch to high-k + metal gate states one of the major cuts since the advent of CMOS technology. Over $ 40$ years $ SiO_{2}$ was the material of choice as gate insulator. The first high-k + metal gate transistors in a high volume manufacturing process were reported in [21]. They showed a working $ 153\,\mathrm{Mb}$ SRAM array with good process yield, performance, and reliability. The transistors were manufactured with a hafnium-oxide gate dielectric Equvivalent Oxide Thickness (EOT) $ 1.0\,\mathrm{nm}$), dual workfunction metal gate electrodes, enhanced channel strain, ultra shallow junctions, and nickel silicide.

Mistry et al. [21] employed a high-k first and metal gate last process. The processing until the salicidation is analog to their $ 90\,\mathrm{nm}$ and $ 65\,\mathrm{nm}$ node [22,23], with the exception of atomic layer deposited hafnium-based high-k dielectric instead of $ SiO_{2}$. After the interlayer dielectric deposition, the poly dummy gates are opened by polishing and subsequently removed, followed by deposition of PMOS workfunction metal and a patterning process removing the PMOS metal from NMOS areas and deposition of the NMOS workfunction metal. The gate ranches are filled with aluminum for low gate resistance and planarized by a metal polishing step. Finally, the contact etch stop layers are deposited. The resulting $ 45\,\mathrm{nm}$ high-k + metal gate transistors incorporate third geneartion strained silicon and feature a $ 25\times$ reduction for NMOS and $ 1000\times$ reduction of gate leakage for PMOS as well as an average drive current improvement of $ 32\,\%$ at the same voltage and $ I_{\mathrm{off}}$ compared to the $ 65\,\mathrm{nm}$ node.

Recently Jan et al. [11] presented a $ 32\,\mathrm{nm}$ System on Chip (SOC) platform technology with a second generation high-k + metal gate and three transistor architectures. This technology is the successor of the previously presented $ 45\,\mathrm{nm}$ technology by Jan et al. [8]. In order to meet the requirements for the different functional circuit blocks of SOC applications the three transistor types offer a logic (High Performance (HP) or Standard Power/Performance (SP)), an ultra Low Power (LP), and a high voltage I/O design, which can be employed simultaneously but optimized independently. The short time ago expensive to implement triple gate architecture has become feasible due to the extremely low gate leakage of the high-k dielectric, allowing a much simpler gate implementation by sharing the same high-k dielectric layers for the logic and the low power transistors. The I/O transistors feature an additional pre-patterned thermal oxide layer underneath the high-k layer to improve the stress tolerance related to high voltage. Furthermore, strained silicon technologies have been employed in the form of tensile contact strain, compressive metal gate fill for NMOS, embedded high $ Ge$ $ SiGe$, and reduced proximity raised source/drain. Overall, this architecture features logic transistors with extremely high drive currents and low leakage in a single chip.

Packan et al. [24] showed a high performance $ 32\,\mathrm{nm}$ logic technology featuring also $ 2^{\mathrm{nd}}$ generation high-k/metal gate and $ 4^{\mathrm{th}}$ generation strained silicon transistors. He reported a $ 28\,\%$/$ 19\,\%$ improvement in $ I_{\mathrm{dsat}}$ and a $ 35\,\%$/$ 20\,\%$ enhancement in $ I_{\mathrm{dlin}}$ over the $ 45\,\mathrm{nm}$ technology for PMOS/NMOS, respectively. The utilized replacement metal gate flow allows to place stress enhancement techniques before the poly gate is removed and has been shown to further increase strain. Furthermore, the variation of the employed $ 32\,\mathrm{nm}$ devices is equivalent to the previous $ 45\,\mathrm{nm}$ technology, which is an important criterion for the required minimum operating voltage for Static Random Access Memory (SRAM) and register file circuits. Good $ V_{\mathrm{ccmin}}$ and the highest reported SRAM density for $ 32\,\mathrm{nm}$ or $ 28\,\mathrm{nm}$ technology were reported. Fully functional $ 32\,\mathrm{nm}$ processors exploiting this technology were demonstrated in January 2009 and are now in volume production.

Figure 2.1: Scheme of a high-k gate stack. By exchanging the $ SiO_{2}$ gate-dielectric with $ H\!fO_{2}$ the
critical oxide thickness of $ \approx 2\,\mathrm{nm}$ for tunneling can be met while keeping control over the channel.

Further scaling demands an even smaller (EOT) ( $ 32\,\mathrm{nm}\rightarrow 8\,$Å and $ 22\,$nm$ \rightarrow 6\,$Å). One possible solution to this problem is to switch from $ H\!fO_{2}$ with $ k_{H\!fO_{2}}\approx25$ to oxides with higher dielectric constants. Frank et al. [25] studied two different metal gate/high-k gate stacks with gate first integration schemes. The first scheme employs a highly nitrided bottom interfacial layer Fig. 2.1 below the hafnium-based dielectric, thus increasing its overall dielectric constant, while the other scheme replaced the hafnium-based dielectric with ``higher-k'' titanium dioxide ( $ k_{TiO_{2}}\approx30-170$ depending on the crystal structure and orientation) and optional barrier layers to impede undesirable oxygen migration [26,27,28]. Good results for the $ Si_{3}N_{4}$ interfacial layer were reported. Amazingly, no adverse effects like reduced mobility or a negative threshold voltage shift due to positive fixed charges were observed. Frank et al. found an (EOT) of $ \sim 6.2$   Å, which is suitable for the $ 22$nm technology node and renders highly nitrided bottom interlayers attractive for scaling hafnium-based gate stacks. The titanium dioxide approach experienced some difficulties in preventing the diffusion of oxygen from $ TiO_{2}$ to the high-k/channel interface. Some of the problems were growth of $ SiO_{2}$ and up-diffusion of oxygen to the poly-$ Si$/$ TiN$ interface, forming $ SiO_{2}$ and creating an additional path for degradation and disintegration. The down diffusion of oxygen can be decreased, but not supressed, by a combination of $ H\!fO_{2}$ and $ Si_{3}N_{4}$ as bottom barrier layer. Furthermore an aluminum oxide bottom and top barriers are only insufficiently blocking oxygen migration [29]. Therefore, in order to allow further scaling more suitable barrier layers and/or metal electrodes which are less susceptible to oxygen in-diffusion are needed.

Another important parameter is the threshold voltage $ V_{\text{t}}$. There are three ways to tune $ V_{\text{t}}$: channel engineering, choosing the right metals (near band edge for high performance applications or slightly off band edge for low standby power applications), and using capping layers in the dielectric. Tseng et al.[30] studied the last method and showed the relevance of the interfacial layer. The threshold voltage is controlled via a dipole induced shift in the effective workfunction. The dipole is formed at the interface between the high-k oxide and the $ SiO_{2}$ interfacial layer [31,32,33]. Tseng et al. proposed that the $ V_{\text{t}}$ tuning is due to the net dipole moment of the $ H\!f-O$ and $ RE-O$ (rare earth) bonds at the high-k/$ SiO_{2}$ interface. This is supported by the correlation between dopant electronegativity, ionic radius, and $ V_{\text{t}}$.

While the above mentioned gate stacks are for use in a switching device in e.g. SRAM (volatile Random Access Memory (RAM)), there is also a huge demand for Non-Volatile Random Access Memory (NVRAM). The most common NVRAM type today is NAND flash memory. Over the last few years the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) gate stack attracted interest, as a possible candidate for flash devices. Therefore I will review both device types and compare them subsequently.

next up previous contents
Next: 2.1.1 Flash Memory Up: 2. Gate Stack Overview Previous: 2. Gate Stack Overview

T. Windbacher: Engineering Gate Stacks for Field-Effect Transistors