Further scaling of the feature size will lead to a modification of the device structure due to the lack of physical space between neighboring cells. This will cause a planarization of the device and a degradation of the coupling factor. To compensate the loss of the coupling capacitance of the sidewalls two approaches are considered. Firstly, by exchanging the Inter Poly Dielectric (IPD) with a high-k material the gate coupling factor is increased and secondly, by replacing the flash ONO gate stack by a SONOS charge trapping gate stack, facilitates a thinner gate stack. For charge trapping devices also high-k materials are needed as Blocking Oxides (BOs) between the trap layer and the control gate (Fig. 2.4). Both applications require high-k materials with large band gaps and band offsets, limiting the materials to choose and restricting the k-values in the moderate range from to . Due to the charge retention specifications for flash-based memory ( years) very low leakage through IPD or the BO is needed. Therefore, the trap density of the high-k dielectric should be as low as possible.
with () is a possible candidate for replacing as IPD and BO in the near future. A substantial improvement in device characteristics for crystalline compared to amorphous has been reported . At crystallizes into the phase, increasing its band gap and band offsets, and localizing its defects in a horizontal band between and . However, the properties of the films (crystallization, texture, and microstructure) have been found to depend strongly on the deposition technique and parameters.
While for the next technology node with a metal control gate may be sufficient, future generations demand higher even -values. Therefore, several dielectrics with higher -values () are under investigation. The improvement in -values must not be at the expense of a reduced band gap or increased trap density. Promissing candidates are aluminates and scandates. For instance, the rare earth scandates and feature higher -values compared to , while maintining at the same time the band gap ( ) and band offset ( with respect to ) over a wide range of compositions. Aluminates such as and rare earth aluminates (e.g. ) inherit a band gap of for their amorphous phase, and are close to amorphous for a wide compositional range, but exhibit a lower than crystalline . Also their band offsets remain independent over a wide compositional range and stay close to amorphous . Additionally, the permittivities of amorphous and vary approximately linearly with composition ( for , and for at an ratio) .
However, also for floating gate devices the interfacial properties are of great importance. Govoreanu et al.  investigated various top gate materials (, , and -poly-) and different processing procedures and found for the used - IPD ( and respectively) the layer as a limiting element for the achievable program window, due to shallow traps and their interaction with the as parasitic Variable Oxide Thickness (VARIOT) gate stack.
Potentially better suited to build ultra-scaled devices are approaches like storing the information in a silicon nanocrystal layer instead of a nitride layer [42,43]. Silicon nanocrystal memories show no erase saturation for small tunnel oxide thickness, deeper electron storage traps ( ), extra local field effects as well as Coulomb blockade (essential to superior Fowler-Nordheim erase characteristics compared to SONOS). The device variability due to the variation of crystal size and distance is not critical due to partial selfordering . Ohba  demonstrated a bulk-planar SONOS type memory with a double tunnel junction, exhibiting good scalability while offering low write/erase voltages and excellent charge retention characteristics at the same time. There are additionally FinFET architectures in SONOS and nanocrystal devices, indicating a promising path way , and investigations for quantum dot materials different to silicon .