Subsections

• 6.1 Motivation
• 6.2 Feature-Scale Simulation
  • 6.2.1 The Deposition Processes Used by Investigations
  • 6.2.2 CMP
  • 6.2.3 Integration
  
  
• 6.3 Backend Simulation
  • 6.3.1 Capacitance Types
  • 6.3.2 Capacitance Models
  • 6.3.3 Interfacing to Circuit Design
  
  
• 6.4 Simulation Results
• 6.5 Void Extraction Step
• 6.6 Optimizing the Voids for the Metal Profiles with Constant Line-to-Line Spacings
• 6.7 Summary

6. Application of ELSA to Interconnect Processes

Key issues of the deposition processes are the geometry, modeling of the source, collision in transit from the source to the feature, and the collision and sticking rate of the material being deposited.

In this chapter we present simulation results for the backend of a 100 $\mathrm{nm}$ process, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack consisting of aluminum metal lines and titanium nitride local interconnects. Feature-scale topography simulations serve here as input to subsequent capacitance extraction. The entirety of simulations and extracted capacitances characterize a specific technology and are made accessible to the circuit designer via a database.

6.1 Motivation

One of the challenges that TCAD must currently meet is the analysis of the performance of groups of components, interconnects, and - generally speaking - large parts of the IC. This enables predictions that the simulation of single components cannot achieve. In this chapter we focus on the simulation of backend processes, interconnect capacitances, and time delays. The simulation flows start from the blank wafer surface and the final result is device information for the circuit designer using circuit simulators such as SPICE (simulation program with integrated circuit emphasis)^6.1.

Interconnects are becoming increasingly important as the shrinking of the semiconductor technologies continues, since the timing delays due to metal lines contribute increasingly to the overall delay. Therefore, it is imperative for predictive TCAD applications that capacitance and resistance of interconnect lines are modeled as accurately as possible.

Most RCX (resistance and capacitance extraction) tools assume rectangular metal profiles, either planar or conformal dielectrics, and they use simplistic void models. Even if the metal slope is modeled, it is mostly assumed constant and independent of space. While these idealizing assumptions may be sufficient for past technologies, they are insufficient for today's technologies like the 100nm process considered in Section 6.4, where interconnects show a number of special features which are nowhere close to ideal.

For proper modeling of the capacitance, one has to know the metal profile, e.g., bottom and top CD s (critical dimension) and metal slope, the profile of the deposited layer with and without CMP, and the profile of the void, if it forms. Generally these three profiles depend heavily on the conditions of the deposition process, on metal thickness and line-to-line spacing, and to a lesser degree on the metal width [8,10].

In order to join topography and backend simulations, deposition, etching, and CMP processes in the various metal lines are used to build up the backend stack starting from the flat wafer surface. Depending on the metal combination, line-to-line spacing, and line width, thousands of simulations are required whose results are stored in a database.

6.2 Feature-Scale Simulation

Figure 6.1: SEM image of a whole backend stack comprised of three Al metal lines M$_{1}$, M$_{2}$, and M$_{3}$, bottom-up, respectively, and a Ti-nitride local interconnect.

Having described the handling of moving boundaries in Chapter 5, this section focuses on the chemical surface reactions. Starting from a plain substrate, the principal topography simulation steps are etching trenches, depositing thin films, and CMP (cf. Figure 6.1). Finally we outline how the single topography simulations are integrated to yield larger backend structures.

6.2.1 The Deposition Processes Used by Investigations

In the considered backend process the deposited films are silicon nitride and silicon dioxide films (cf. Section 6.4). Here the transport of particles happens in the radiosity regime and the deposition processes are governed by luminescent reflection.

The silicon nitride films were deposited by PECVD (plasma enhanced CVD) from silane and NH$_3$ and were not doped. The chemical reaction is $\textrm{SiH$_4$}\xspace + \textrm{NH$_3$}\xspace \overset{}{\rightarrow} \textrm{SiNH} + 3 \textrm{H$_2$}\xspace$ [74]. For simulation purposes this was considered as the essential reaction, a detailed model including triaminosilane condensation can be found in [94]. The silicon dioxide film is deposited from a TEOS process which has been treated in Chapter 4.

In order to calculate the thickness $\Delta d$ of the film deposited during a time interval of length $\Delta t$, we observe that $\Delta d$ is proportional to $\Delta t$, to an Arrhenius term, and to the deposition rate $R$ corresponding to the chosen deposition model. This implies $\Delta d = \Delta t \cdot k_e \mathrm{e}^{-E/kT} \cdot R$. Here $k_e \mathrm{e}^{-E/kT}$ is the Arrhenius term with activation energy $E$, absolute temperature $T$, a pre-exponential constant $k_e$, and $R$ is the deposition rate [67].

When modeling topography processes it is generally possible to write down complicated reaction paths and list dozens of possible surface reactions. However, it is not straightforward to determine the vital reactions and their constants. Thus it is important to reduce the possible reaction paths to an essential minimum (cf. Chapter 4).

Figure 6.2 shows the simulation result for the process mentioned above which has been used for the calculation of capacitance.

Figure 6.2: Simulation of the deposition process used for a line-to-line spacing of $\mathrm{0.45\mu m}$.

6.2.2 CMP

On the feature-scale level the simulation of CMP can be performed in a straightforward manner, since the thickness of the remaining part of the layer is known. In this simulation step the boundary is modified so that all parts above the given thickness are removed and the remaining points are joined accordingly.

6.2.3 Integration

Figure 6.3: M$_{3}$ lines ( $0.5\mathrm{\mu m}$ top width) at $0.45\mathrm{\mu m}$ line-to-line spacing above the M$_{2}$ plane. Cap oxide was deposited (thin layer surrounding M$_{3}$ lines) before the top nitride (thick layer) was deposited. Void formation occurs between the lines.

Figure 6.4: M$_{3}$ lines ( $0.5\mathrm{\mu m}$ top width) at $0.90\mathrm{\mu m}$ line-to-line spacing above the M$_{2}$ plane. The voids are smaller than in Figure 6.3.

Figure 6.5: M$_{3}$ lines ( $0.5\mathrm{\mu m}$ top width) at $1.50\mathrm{\mu m}$ line-to-line spacing above the M$_{2}$ plane. In this case the voids formed are quite small.

Figure 6.6: This figure shows the two-dimensional schematics of a signal line (middle) surrounded by grounded lines and planes. The total capacitance equals the sum of twice the coupling capacitance plus top and bottom capacitances.

Simulations of single features, performed by the above steps, can be duplicated using affine transformations $\mathbf{x}\mapsto A\mathbf{x}+ \mathbf{b}$ to obtain more complex structures. For example, to arrive at the structures shown in Figures 6.3, 6.4, and 6.5, it is necessary to simulate the processes for a single feature including etching and subsequent deposition. The resulting boundaries are duplicated by affine transformations. At the left and right boundaries, other simulations have to be performed, as they are formed by half trenches. The results for the left hand boundary are mirrored to yield the right hand boundary.

6.3 Backend Simulation

The coordinates of the structures simulated by topography simulator serve as input to calculate the electric filed. For the following simulations RAPHAEL [7] was used. RAPHAEL is a solver for electrical field and calculates the charge densities and various capacitances. Depending on the required resolution, the simulator yields a large number of points describing ILD (interlevel dielectrics) and voids. Since this number of surface elements determines the number of RAPHAEL grid points and simulation time is an important factor, a significant reduction of the number of points is necessary. Otherwise simulation times would be orders of magnitude larger than those of equivalent simplified structures. Hence we use a surface-coarsening algorithm to rework the output and to reduce the number of points supplied to the RAPHAEL [36].

6.3.1 Capacitance Types

A typical multi-level interconnect structure consists of one layer containing a few parallel conductors at different voltages, embedded and electrically isolated from each other by dielectric materials, closed at the top and at the bottom by two other metal layers consisting of other parallel conductors or by ground planes. Such structures are used to extract the total and mutual capacitance per unit length of each conductor. The calculated capacitance is then used for the worst-case evaluation of the integrity parameters of the interconnect structure such as cross-talk and propagation delay. This parameters are dependent on materials and on the geometry of the structure, e.g., number of conductors and their spacing and width.

For example one can assume that a signal line is at high voltage and surrounded by two lines on the left, two lines on the right, a plane underneath, and, if necessary, a plane above. The surrounding lines and planes are assumed to be grounded. For example an M$_{2}$ signal line could be surrounded by M$_{2}$ grounded lines above the M$_{1}$ plane and underneath the M$_{3}$ plane. This skeleton is shown in Figure 6.6.

6.3.2 Capacitance Models

Capacitance simulations are performed depending on three variables: First, they depend on the combination of metals. The number of these combinations can be high for a six-layer technology [21,17].

The second variable is line-to-line spacing. Simulations start from the minimum allowed line-to-line spacing (e.g., $0.14\mathrm{\mu m}$) and end in the range of a few microns (e.g., $6\mathrm{\mu m}$). Generally, initial line-to-line spacing increments are fine to capture the strong dependence of the capacitance on line-to-line spacing, while the final increments are coarse to capture capacitance saturation.

Third, capacitance simulations depend on the line width. Simulations start from the minimum allowed width to approximately 60 times the minimum width. Since the dependence on width is well behaved, only a few intermediate widths are usually needed.

6.3.3 Interfacing to Circuit Design

First the designer instantiates a capacitance element, e.g., for an M$_{3}$ line above the substrate. The designer must then specify the metal type and the surrounding planes as well as metal width, length, and line-to-line spacing. Then the designer creates a SPICE input file. Finally the database and the designer's options are read, the capacitor of interest is located, line-to-line spacing and width are interpolated or extrapolated, and the capacitance instance with a numeric value for the capacitance at that node is replaced. Now the designer can run the SPICE program and observe circuit performance. If timing requirements are not met, the designer changes the properties of the capacitance, e.g., makes it narrower for lower capacitance, and repeats the process.

6.4 Simulation Results

In order to verify ELSA, different interconnect and metal lines structures provided by our industry partner have been considered to be simulated. As an example, we consider the case of M$_{3}$ lines above the M$_{2}$ plane. These backend stacks are part of a 100nm Aluminum/TEOS process (cf. the SEM image shown in Figure 6.1). The films deposited are silicon nitride and silicon dioxide films and the interconnect lines are made of aluminum. The experiments performed during the development of a RAM process were performed in a LAM 9600 reactor [12].

The M$_{3}$ lines have a width of $0.50\mathrm{\mu m}$, and a line-to-line spacing varying between $0.45\mathrm{\mu m}$ and $1.9\mathrm{\mu m}$. Figure 6.3 shows the RAPHAEL structure constructed from ELSA coordinates at minimum line-to-line spacing. Note that at a minimum line-to-line spacing the metal lines are vertical and voids have their maximum size. For a line-to-line spacing of $0.9\mathrm{\mu m}$, as shown in Figure 6.4, the side walls are sloped and the voids are considerably smaller.

Next we build the structure with a line-to-line spacing of $1.5\mathrm{\mu m}$. Figure 6.5 shows the corresponding RAPHAEL structure, again constructed from simulation results. Note that in this case, however, the metal lines have a larger slope, which duplicates the real process geometry. Voids are quite small in this case. At $1.9\mathrm{\mu m}$ line-to-line spacing the metal slope has saturated and no voids are formed.

Figure 6.7: This figures compares the M$_{3}$ middle line capacitance as a function of line-to-line spacing between simulations and measurement.

Figure 6.8: This figures compares the M$_{2}$ middle line capacitance as a function of line-to-line spacing between simulations and measurement.

The capacitance of the middle line was simulated for the above structures and compared to CBCM s (charge based capacitance measurement)^6.2. The simulation results and measurements are compared in Figure 6.7. Simulation results show very good agreement with data obtained from measurements with a maximum error below 4%.

As a second example, we compare the capacitances extracted after silicon dioxide deposition in the M$_{2}$ plane to CBCM s. Simulations were performed for line-to-line spacings of $0.3\mathrm{\mu m}$, $0.6\mathrm{\mu m}$, $1.0\mathrm{\mu m}$, and $2.0\mathrm{\mu m}$. The simulated and measured capacitances are shown in Figure 6.8 and again the error is below 4%.

The two-dimensional models for lines surrounded by other lines, as shown by these examples, are important since there is an abundance of cases where they appear on a chip. One of the most important cases is the last layer of the metal lines which are used as paths from one side of the chip to the other. Such an example is a TCO (total cost of ownership) path whose length is $22 000 \mathrm{\mu m}$ in a 72Mbit DRAM chip which is $1 \mathrm{cm}$ in length. The TCO path is divided into eight portions, each portion has a different width and different spacing to adjacent lines. It is very important that this path is modeled accurately and optimized, as it is used to fabricate products working at high operation frequency. To predict and optimize the performance of this line, very accurate models are needed motivating these simulations.

6.5 Void Extraction Step

Figure 6.9: Void extraction at the end of simulation and right after the formation of the void by aspect ratio$=$1 for axes.

Figure 6.10: Void extraction at the final and the void formation step of the simulation by aspect ratio$\neq$1 for axes.

Depending on the resolution of the grid which is used by ELSA during the deposition processes, ELSA may yield a large number of points to describe a void. This number of void points determines the number of grid points used by RAPHAEL and subsequently the simulation time. Although, we have used a coarsening algorithm to reduce the number of points that represent the boundary or voids, we could have obtained a much lower number of points if we had extracted the void at a different simulation step, namely, just after the formation of the void. The standard method also used in [80] is to extract the void at the end of the simulation. From the point of view of the speed function the void has to be frozen in its place once it has formed. Therefore, it must not matter when we extract the void, i.e., at the end of the simulation or immediately after the void formation, but the different points in time when the void is extracted have produced different void profiles. Figure 6.9 shows the extracted voids at these different points in time where the aspect ratios between the axes is one. It is very difficult to discern any difference of the two voids. To more clearly see the difference, we have changed the aspect ratio between the axes to a different ratio which is not equal to one. This is shown in Figure 6.10.

This difference originates from the extension of the speed function. Practically once a void forms, there is no more visibility between the void and source of deposition and the void and the deposited boundary, as well. Therefore, it is expected that the void is no longer displaced. However, depending on the width of the narrow band and the duration of a time step some points of the void do not leave the narrow band for a few simulation cycles and their adjacent grid points are assigned a non zero speed value during the extension of the speed function. This continues until the void is no longer inside the narrow band and leads to the change of shape of the void compared to its shape just after its formation.

As can be seen clearly in Figure 6.10, the form of the void extracted at the final step of the simulation is unrealistic since it contains steps which are not seen in the measurements. In addition, by extracting the void immediately after its formation, redundant points along vertical segments are eliminated and the subsequent coarsening is no longer required. However, the difference between the shapes does not influence the accuracy of the capacitance calculations and demands only additional simulation time due to the coarsening algorithms.

The immediate advantage of knowledge obtained from this study was a high reduction of the time of simulations achieved by our industry partner for further capacitance calculations in two dimensions because they are investigating a great number of simulations. Furthermore, this knowledge has been used by implementation of three-dimensional ELSA where the number of void points are drastically more than in two dimensions and each reduction of point number plays a very important role to make the simulator more efficient.

6.6 Optimizing the Voids for the Metal Profiles with Constant Line-to-Line Spacings

The effects of changing line-to-line spacing with varying slopes has been studied in the previous sections. In this section we focus on the other geometrical effects considering different metal profiles to further optimize the voids in order to reduce the capacitance of conductors. Figure 6.11 shows the simulation result of different metal profiles. The first profile is an rectangular trench which is considered as a reference. The line-to-line spacing is constant for all profiles. The metal profiles after the reference profile from left to right are considered for the effect of outward slope, hard mask, inward slope, cap layer, and undercut.

Here one can see the advantage of the line source model presented in Section 4.1.1. As mentioned there, the model enables to simulate a set of trenches simultaneously compared to models used in our first attempts in [19,35].

Figure 6.12 shows the different voids which have formed during the deposition of material into the metal profiles as shown in Figure 6.11. The interesting effect can be seen during the void formation into a profile with a hard mask. The hard mask considerably reduces the size of the void and continuously shifts the bottom of the void to a higher position.

According to the simulations presented in the previous sections one still expects to see the largest void during the deposition of material into a vertical structure. Although this is not a very wrong expectation, but these new simulations show that the largest and smallest voids are formed at profiles with inward- and outward slopes, respectively.

The strange form of the void obtained from the profile with undercutting originates from the fact that there is no visibility from the source to the line segments located at the undercut regions.

The other effects which are important to our industrial partner are the influence of slopes with varying top CD from $50\mathrm{nm}$ to $15\mathrm{nm}$. Figure 6.13 shows the simulation of the deposition of material into this varying top CD. The simulations have shown interesting effects. Whereas the position of the top of the voids does not change, the bottom of the voids is shifted upwards as the top CD is decreased. This can be seen more clearly in Figure 6.14.

6.7 Summary

Topography and RCX simulation were joined to predict the timing delays in the backend stacks of a 100nm CMOS process for memory cells. A rigorous simulation approach such as the one presented is indispensable for today's technologies since timing delays become increasingly important due to shrinking. The complex interconnect structures are built from the structures at the feature scale yielding many configurations depending on the different metal combinations, line-to-line spacing, and line width. The interconnect structures serve as input to the electric field calculator, in this case RAPHAEL, whose results from the capacitance simulations are stored in a database. The circuit designer accesses the results of this simulation flow and uses them in SPICE circuit simulations. The significant influence of void formation on the capacitances was quantified, as using voids in a controlled and reproducible manner can be an economically advantageous substitute for low-$k$ materials. The simulations show very good agreement with CBCM s and hence they play a significant role during the development of backend processes and circuit design.

Figure 6.11: Deposition simulation for studying the effects of different shapes of trenches.

Figure 6.12: Void characteristics during the deposition simulation shown in Figure 6.11.

Figure 6.13: Deposition simulation for eight different slopes and top $CD$.

Figure 6.14: Void characteristics during the deposition simulation shown in Figure 6.13.

Foonotes

... emphasis)^6.1

SPICE is a program that simulates electronic circuits and calculates voltages and currents versus time (transient analysis) or versus frequency (AC analysis). Most SPICE programs also perform other analysis like DC, sensitivity, noise and distortion. SPICE is available from many vendors who have added schematic drawing tools to the front end and graphics post processors to plot the results. SPICE simulators and applications have expanded to analog and digital circuits, microwave devices, and electromechanical systems.

... measurement)^6.2

CBCM is an often used technique which provides a simple way for measuring the overall parasitic capacitance of on-chip interconnects[95].