Yury Illarionov MSc PhD Dr.techn. Publications

Biography Yury Illarionov was born in Leningrad (now Saint-Petersburg) in 1988. He studied solid state physics at the Physical Science and Technology Faculty of St. Petersburg State Polytechnical University where he received the B.Sc. and M.Sc. degrees in 2009 and 2011, respectively. From 2010 to 2012 he studied advanced material science in Grenoble Institute of Technology (France) and University of Augsburg (Germany) in frameworks of Functionalized Advanced Materials and Engineering (FAME) Erasmus Mundus program and in September 2012 received a double European M.Sc. degree. His scientific carrier has started in October 2007 in Ioffe Physical-Technical Institute (Russia) and in November 2011 he joined the PhD program there. He also visited IRCELYON (France, May-July 2011) and Singapore Institute of Manufacturing Technology (Singapore, February-July 2012) as a young guest researcher. He joined the Institute for Microelectronics in February 2013. In January 2015 he received the PhD degree in semiconductor physics from Ioffe Physical-Technical Institute and in December 2015 the Dr.techn. degree from TU Wien. Since January 2016 Dr. Yury Illarionov is a postdoc researcher working on reliability of the next-generation 2D FETs with graphene, MoS2 and phosphorene.

Encapsulation of molybdenum disulfide (MoS₂) field-effect transistors (FETs) presents an important step towards top-gated devices that are required for circuit integration. This is because the insulators employed to protect the channel from the ambient environment can be subsequently scaled and used as top-gate insulators. However, encapsulation layers themselves can also degrade device performance. For example, encapsulation can increase device-to-device variability, reduce the mobility or cause undesired shifts in the threshold voltage. We have recently attempted to understand the impact of the encapsulation scheme on the performance and stability of MoS₂ FETs with a 30 nm thick Al₂O₃ gate insulator (Fig. 1a) grown by atomic layer deposition.

To do this, we studied the devices encapsulated using four different schemes, namely Al₂O₃, Al₂O₃/Parylene N, Parylene N/Al₂O₃/Parylene N and Parylene C/Al₂O₃/Parylene N (Fig. 1b). In all cases, the growth of Al₂O₃ was performed at 200 ^oC, while Parylene N or C was deposited after 3 hours of annealing at 130 ^oC followed by 12 hours of pumping. Similar to previous literature, our results show that the I_D-V_G characteristics of MoS₂ FETs with Al₂O₃ encapsulation have a strongly negative V_th (Fig. 2a) due to the n-type doping of the channel by positive charges inside the Al₂O₃. At these negative gate voltages, there is a substantial thermionic leakage current, which leads to a reduced on/off current ratio of only about 10⁶. In contrast, the use of Parylene N/Al₂O₃/Parylene N encapsulation makes V_th considerably more positive and thus allows one to achieve on/off ratio values of up to 10¹⁰ (Fig. 2b). Furthermore, our MoS₂ FETs with Parylene N/Al₂O₃/Parylene N encapsulation are not sensitive to the ambient environment and exhibit excellent stability after annealing at 165 ^oC (Fig. 2c), as well as the smallest variability in performance parameters. Thus, the use of a Parylene N/Al₂O₃/Parylene N encapsulation scheme offers an important step towards highly stable MoS₂ FETs. However, further steps are required to optimize device processing by avoiding air exposure in between device fabrication and encapsulation.

Fig. 1: (a) Schematic layout of our MoS₂ FETs. (b) Typical I_D-V_G characteristics of our devices with different encapsulation schemes. Pure Al₂O₃ introduces a strong negative shift of V­_th.

Fig. 2: I_D-V_G characteristics of 22 devices with (a) Al₂O₃ and (b) Parylene N/Al₂O₃/Parylene N. The use of Parylene N makes V_th more positive, which results in on/off current ratios of up to 10¹⁰. (c) Simultaneously, the I_D-V_G characteristics of Parylene N/Al₂O₃/Parylene N encapsulated devices remain similar in the ambient environment and in the vacuum before and after annealing.