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2 System Model

In this work we use a simple model of a homogeneous digital system as shown in Fig. 2. Per clock cycle, each gate output node is switching with a certain probability, i.e. the activity ratio a. The number of stages between two latches is the logic depth ld.

**Figure 2:** Digital VLSI system model
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Further system parameters are F_io, L_M, and c_M which are the average fan-in/fan-out, average interconnect length, and interconnect capacitance per length. Primary operating parameters are V_DD,nom, L_nom, T_nom, and f_c,nom which are the nominal supply voltage, gate length, operating temperature, and clock frequency. Furthermore, to enable investigations based on just one device type (e.g., the NMOS transistor), all analyses can be carried out assuming symmetric (but statistically independent) transistors. For clarity, most equations are only given for the single-device-type case.

G. Schrom, V. De, and S. Selberherr: VLSI Performance Metric Based on Minimum TCAD Simulations