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6 Power Consumption

Sum total of dynamic and static power consumption, and the switching energy per transistor are modeled as [2]

$\begin{displaymath} P= P_{dyn}+ P_{stat} = af_{c}V_{DD}^2 C_L+ V_{DD}I_{off} \end{displaymath}$

(5)

and

$\begin{displaymath} E_s= \frac{P}{af_{c}} = V_{DD}^2C_L+ V_{DD}I_{off}\frac{1}{af_{c}} \end{displaymath}$

(6)

neglecting the crow-bar current during the switching transient, which is usually applicable. The switching energy is the energy per transistor switching and is therefore independent of the system architecture. However, activity ratio and logic depth (the latter via f_c,max, cf. (4)) affect the tradeoff between power consumption and speed significantly. According to the system model the power delay product is related to the switching energy as $Pt_d= E_s\!\cdot\!af_{c}t_d$ .

G. Schrom, V. De, and S. Selberherr: VLSI Performance Metric Based on Minimum TCAD Simulations