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7 Noise Margins, Inverter Gain, and Output Swing

The determination of the static noise margins NMH, NML would require circuit simulation of an inverter. A close estimate of the noise margins can be determined from just two DC simulations (4a, 4b). Exploiting the fact that the input voltages VIH, VIL will be around VDD/2 and that one of the output transistors is in saturation, the following algorithm can be used to determine the noise margins: The currents and conductances at the critical voltages (i.e., where the inverter gain is |Ainv|=1) are estimated by scaling two IV curves according to Fig. 6. With I1(V) = ID(VG=V,VD=VDD/2), I2(V) = ID(VD=V,VG=VDD/2), and Isc= I1(VDD/2) = I2(VDD/2) the critical voltages VIL, VOH can be obtained by solving:


\begin{displaymath}\aatrue {\renewcommand {\arraystretch}{1.6} \begin{array}{r... ...dot \frac{I_1(V_{DD}-V_{IL})}{I_{sc}} \end{array} }\aafalse \end{displaymath} (7)

The input-low noise margin NML is then

 \begin{displaymath} NM_L= \frac{V_{IL}-(V_{DD}-V_{OH})}{V_{DD}} \end{displaymath} (8)

and the input-high noise margin is determined accordingly. In the case of a single-device analysis the inverter transfer curves are symmetrical and the noise margins are NML= NMH= NM. The noise margins of gates can be estimated also by scaling the currents I1, I2 according to the fan-in and the logic style (e.g., for a static-logic NAND gate with a fan-in of Fin we obtain $\tilde{I}_1 = I_1/F_{in}, \, \tilde{I}_2 = I_2\!\cdot\!F_{in}$ ). Inverter gain and output voltage swing are determined as $ A_{inv}= g_{m}/g_{o}\bigr\vert _{V_G=V_D=V_{DD}/2} $   and OS= (VDD- 2 IoffRon)/VDD   from 4a/4b and 2/5a respectively.


  
Figure 5: Definition of static noise margins and output swing
\begin{figure} \epsfysize=6cm \centerline{\epsfbox{nm-def.eps}}\end{figure}


  
Figure 6: Extraction of static noise margins
\begin{figure} \epsfysize=6cm \centerline{\epsfbox{nm-sim.eps}}\end{figure}

next up previous
Next: 8 Application Up: VLSI Performance Metric Based Previous: 6 Power Consumption

G. Schrom, V. De, and S. Selberherr: VLSI Performance Metric Based on Minimum TCAD Simulations