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1. Introduction

In the last four decades, Si has established itself as the fundamental material for manufacturing a large number of semiconductor devices. The abundance, thermal stability and the formation of a natural native oxide makes Si the suitable choice for developing complementary metal oxide semiconductor (CMOS) integrated circuits for electronic applications. Moreover, the success of CMOS technology is largely due to the fact that the MOS transistors can be scaled to increasingly smaller dimensions.

CMOS technologies have witnessed aggressive reduction of the feature size down to the sub 100 nm regime thereby delivering increased performance in terms of higher integration densities, increased speed and lower power consumption. However, further down sizing of the feature size to the deca nanometer regime becomes more challenging with each successive CMOS technology node as fundamental technological and physical limits of existing processes and materials are reached. Key factors that prevent the forever continuous scaling of CMOS devices are [Rairigh05,Brillouët06,Haensch.06]:

  1. The limitations associated with lithography. The continuous advancements in the lithographic techniques have come primarily from scaling of the wavelength (436 nm in the 1980's to 248 nm in the 1990's to 193 nm). A further reduction of the wavelength to 157 nm and to 13.5 nm for the next generation EUV lithography, however, faces several technical and economical challenges.

  2. Due to the increasing dominance of non ideal effects with each successive technology node, the performance gain is reduced. This coupled together with the increasing costs of process development could further slow down scaling.

  3. Off state power consumption which is caused by junction leakage, gate induced drain leakages (GIDL) and drain induced barrier lowering (DIBL), threshold roll-offs, and gate tunneling currents. With decreasing gate lengths, the leakage currents increase exponentially [Nowak02] thereby making the passive power a significant part of the total power balance. Since there is a fixed amount of power that can be provided or taken away from the chip, tradeoff must be made between the active and passive power and performance.

  4. The customary decrease in the source and drain junction depths, essential for improving short channel effects in ultra scaled devices, leads to an increase in the source/drain series resistances. Thus the device performance may not necessarily be improved [Thompson98].

Given the restrictions associated with further reductions of the gate length, possible solutions fall into two broad categories: a) introducing structural changes into the transistor, and b) seeking new materials and material modifications. Novel device geometries such as FinFETs, multiple gate MOSFETs and ultra-thin body MOSFETs are promising and could provide the means for continued scaling inline with the ITRS roadmap. Similarly, on the materials side, high-k materials such as Hafnium-based dielectrics [Kirsch06,Chau04] in conjunction with alternative gate materials have shown promising results in demonstrating high performance devices [Majhi06,Chau04], and are considered favorable for scaling. Since the drain current of a MOSFET is proportional to the mobility of the carriers, an alternative choice of improving the device performance while keeping other dimensions constant is through the enhancement of the carrier mobility in the conducting channel. This effect is crucial since the mobility in scaled devices is significantly degraded due to the presence of high vertical fields. In this context, strain engineering has come into limelight as a technique for enhancing the mobility.

Starting with the 90nm technology node, strain engineering has become a critical feature in CMOS technology since it can increase the drain current without reducing the transistor channel length. Furthermore, the technique is compatible with other novel device architectures such as multiple gate or ultra-thin body structures to deliver larger drive currents. However, in order to investigate and design strained Si based device structures, it is necessary to model the carrier mobility in these devices. This thesis is devoted to the study of the effect of strain on the electron mobility. The aim is to develop analytical mobility models by incorporating new physical effects that arise from strain. The models are implemented in a general purpose device simulator, MINIMOS-NT, which is then used to investigate the performance of a novel strain based device structure.

The layout of the thesis is as follows. Chapter 2 gives an overview of the different technologies for introducing strain into the Si channel. A brief chronology of the evolution of strained Si technology is outlined and methods such as substrate-induced strain, local strain and external mechanical strain are described. The effect of strain on the electronic band structure of Si is described in Chapter 3. After reviewing the basic concepts of the theory of elasticity, the strain-induced modifications of conduction and valence bands are discussed for different stress configurations, based on the linear deformation potential theory. The effect of shear stress on the band structure is summarized. Since a consequence of strain is a change in the carrier mobility, it is essential to accurately model the mobility for device simulation purposes. An overview of the different mobility models is presented in Chapter 4. In this section comprehensive models for the low and high field bulk electron mobility in strained Si are derived. Efforts to model the inversion layer mobility are also discussed. Finally in Chapter 5, the analytical models are calibrated against Monte Carlo simulation using analytical and full-band simulations. The path of model implementation into MINIMOS-NT as well as interfacing of the strain distribution from device structure into the device simulator is also outlined. It is then applied to calculate the effective mobility versus the effective field. As an example, a novel device structure, the so called dotFET, is examined using drift-diffusion simulations.

next up previous contents
Next: 2. Strained Si Technology Up: Dissertation Siddhartha Dhar Previous: Constants

S. Dhar: Analytical Mobility Modeling for Strained Silicon-Based Devices