Although the effect of stress on carrier mobilities in Si has been known for decades[Smith54], its adoption for improving the device performance was demonstrated only recently by the fabrication of modulation doped Si/SiGe nMOS transistors [Ismail91a,Ismail91b]. The fabrication of these transistors relied heavily on epitaxial deposition of SiGe onto Si substrates, which was brought after years of advancement in the crystal growth technologies such as molecular beam epitaxy and chemical vapor deposition [Kasper75,Bean87]. The knowledge of generating strain in Si was transferred almost immediately from the modulation doped transistors to the mainstream CMOS transistors with Welser and co-workers [Welser92] reporting a more than 100% enhancement in electron mobilities in strained Si layers grown on relaxed SiGe substrates. Since then the field has made tremendous leaps and bounds, with innovative ideas of introducing stress into the channel with each technology node.
This chapter gives an overview of the different techniques of introducing stress into Si. These methods can be broadly classified into three different categories. These are a) substrate-induced strain introduced globally over the entire substrate, b) local strain arising from different processing steps, and c) external mechanical strain also known as package strain. The different stress-inducing mechanisms are summarized in Fig. 2.1.