next up previous contents
Next: 2.3 Carrier Generation and Up: 2. Simulation of Semiconductor Previous: 2.1 Classical Semiconductor Device


2.2 Analytic MOSFET Approximations

For the simulation of electronic circuits it is often of interest to have compact models for the involved devices. In comparison to solving the semiconductor device equations using compact models reduces the simulation time drastically. Compact models can also be a good guide on what effects the change of physical quantities has on the device characteristics.

The disadvantage is that for each device the right model has to be chosen and the according model parameters have to be extracted. Furthermore, it is not possible to investigate novel device geometries or new materials without processing the device and obtaining an adequate model first.

2.2.1 Interface and Oxide Charges

A change in the interface and oxide charges ( $\Delta\ensuremath{Q_\textrm{it}}$ and $\Delta\ensuremath{Q_\textrm{ox}}$) contributes to a threshold voltage shift \ensuremath {\Delta V_\textrm {th}} as
\ensuremath{\Delta V_\textrm{th}}= \frac{\Delta \ensuremath{Q_\textrm{it}}+ \Delta \ensuremath{Q_\textrm{ox}}}{C'}   ,
\end{displaymath} (2.31)

where $C'$ is the capacitance per unit area of the oxide.

In the context of NBTI interface charges are usually the result of charged interface defects \ensuremath {D_\textrm {it}}. The interface charge depends on the Fermi-level \ensuremath{\ensuremath{E}_\textrm{F}} and the trap occupancy $f$ and can be calculated as [4]

\ensuremath{Q_\textrm{it}}= \ensuremath {\textrm{q}_0}\int ...
...ath{E}_\textrm{F}},\ensuremath{E})\mathrm{d}\ensuremath{E}  .
\end{displaymath} (2.32)

Charged oxide traps \ensuremath{D_\textrm{ox}} contribute to the threshold voltage shift depending on their position in the dielectric. The resulting, effective, \ensuremath {Q_\textrm {ox}} can be evaluated as [5]
\ensuremath{Q_\textrm{ox}}= \ensuremath {\textrm{q}_0}\int ...
\mathrm{d}\ensuremath{E}  .
\end{displaymath} (2.33)

Here, \ensuremath{t_\textrm{ox}} is the oxide thickness.

2.2.2 The Basic Models

A very common compact model for the MOSFET is the Level 1 model implemented in the circuit simulator SPICE. There the threshold voltage is obtained as
\ensuremath{V_\textrm{th}}= V_\mathrm{T0} + \gamma \left( \...
...nsuremath{Q_\textrm{it}}+ \ensuremath{Q_\textrm{ox}}}{C'}   ,
\end{displaymath} (2.34)

where $V_\mathrm{T0}$ is the threshold voltage for $\ensuremath{V_\textrm{bs}}=0 $V and $\gamma$ the body-effect parameter, defined as
\gamma = \frac{\sqrt{2 \varepsilon_\mathrm{S} \ensuremath {\textrm{q}_0}N_\mathrm{A}}}{C'}   .
\end{displaymath} (2.35)

Here, $\varepsilon_\mathrm{S}$ is the permittivity of the silicon substrate and $N_\mathrm{A}$ the acceptor doping concentration. The potential in the neutral p-type region $\phi_p$ is evaluated as
\phi_p = \frac{\ensuremath{\textrm{k$_\textrm{B}$}}T}{\ensu...
...{q}_0}}\ln\frac{N_\mathrm{A}}{\ensuremath {n_\textrm{i}}}   .
\end{displaymath} (2.36)

During NBTI stress this threshold voltage is shifted due to trapped charges by \ensuremath {\Delta V_\textrm {th}} obtained from (2.31).

In the linear regime, where

\ensuremath{V_\textrm{gs}}> \ensuremath{V_\textrm{th}}\quad...
...m{ds}}< \ensuremath{V_\textrm{gs}}- \ensuremath{V_\textrm{th}}
\end{displaymath} (2.37)

the drain current is obtained as
\ensuremath{I_\textrm{ds}}= \mu C' \frac{W}{L_\mathrm{eff}} ...{V_\textrm{ds}}(1 + \lambda \ensuremath{V_\textrm{ds}})   .
\end{displaymath} (2.38)

Here, $\mu $ is the effective carrier mobility, $W$ the device width, $L_\mathrm{eff}$ the effective gate length, and $\lambda$ is an empirical parameter reflecting the channel length modulation.

In the saturation regime, where

\ensuremath{V_\textrm{gs}}> \ensuremath{V_\textrm{th}}\quad...
...m{ds}}< \ensuremath{V_\textrm{gs}}- \ensuremath{V_\textrm{th}}
\end{displaymath} (2.39)

the drain current is modeled as
\ensuremath{I_\textrm{ds}}= \frac{\mu C'}{2} \frac{W}{L_\mat...
..._\textrm{th}})^2 (1 +
\lambda \ensuremath{V_\textrm{ds}})   .
\end{displaymath} (2.40)

2.2.3 NBTI Related Models

In NBTI investigations the degradation of the transconductance \ensuremath{g_\textrm{m}} is an important figure of merit. The transconductance is defined as the change of drain current as a result of a change in the gate voltage
\ensuremath{g_\textrm{m}}= \frac{\Delta \ensuremath{I_\textrm{d}}}{\Delta \ensuremath{V_\textrm{g}}}   .
\end{displaymath} (2.41)

Devine et al. proposed a transconductance shift versus interface trap ( $\ensuremath{N_\textrm{it}}$), relation as [6]

\Delta\ensuremath{g_\textrm{m}}= \ensuremath{g_\textrm{m0}}...
...emath{N_\textrm{it}}}{1+\alpha\ensuremath{N_\textrm{it}}}   ,
\end{displaymath} (2.42)

where $\alpha$ is a processing related parameter. As mobility model Devine proposed
\mu = \frac{\mu_0}{1+\alpha\ensuremath{N_\textrm{it}}}   .
\end{displaymath} (2.43)

With respect to modeling of NBTI these equations show very well how, for example, a reduction of the carrier mobility reduces the drain current, as does an increase of the threshold voltage.

next up previous contents
Next: 2.3 Carrier Generation and Up: 2. Simulation of Semiconductor Previous: 2.1 Classical Semiconductor Device

R. Entner: Modeling and Simulation of Negative Bias Temperature Instability