5.1.5 Alternative Dielectrics for MOS Transistors

It has been outlined in Section 2.2.4 that the further reduction of device dimensions makes the introduction of alternative dielectric materials necessary. Since none of the possible materials forms a native oxide on silicon, a thin interfacial layer of SiO

can hardly be avoided. Thus, a two-layer band edge diagram is commonly assumed, as depicted in Fig. 5.18 [259].

**Figure 5.18:** Band energy diagram of a stacked dielectric consisting of a thin underlying interface layer and a thick layer of a high- $\kappa$ material with higher dielectric permittivity, but lower barrier height.
$\includegraphics[width=.5\linewidth]{figures/onstack}$

A wide variety of high- $\kappa$ materials can be considered as alternative dielectrics. However, several points must be considered when evaluating these materials:

The dielectric permittivity $\kappa$ .
The barrier height for electrons q $\Phi_\mathrm{e}$ and holes q $\Phi_\mathrm{h}$ on silicon. These values are equivalent to the band edge offsets $\Delta \ensuremath {{\mathcal{E}}_\mathrm{c}}$ and $\Delta \ensuremath {{\mathcal{E}}_\mathrm{v}}$ .
The thermodynamic stability of the dielectric material on silicon: The material must withstand all following processing steps.
The quality of the interfaces: High interface roughness may cause increased scattering which reduces the carrier mobility in the channel.
The trap concentration which leads to trap-assisted tunneling.
The feasibility and integrability of the deposition method in the fabrication process.

Only the permittivity, the trap concentration, and the barrier heights influence the tunneling current. When looking at the barrier height and permittivity of various dielectrics in Table 5.1, one notices a strong trade-off between the barrier height and the dielectric permittivity: dielectrics with a high energy barrier have a low permittivity and vice versa, see Fig. 5.19. Hence, optimization becomes necessary to find the optimum material.

Table 5.1: Band gap energy and conduction band offset of various dielectric materials.

	$\kappa / \kappa _0$	Band gap $\ensuremath{{\mathcal{E}}_\mathrm{g}}$	Conduction band	Valence band	Reference
			offset $\Delta \ensuremath {{\mathcal{E}}_\mathrm{c}}$	offset $\Delta \ensuremath {{\mathcal{E}}_\mathrm{v}}$
	[]	[eV]	[eV]	[eV]
SiO	3.9	9.00	3.00	4.90	[260]
	3.9	9.00	3.50	4.40	[261]
	3.9	9.00	3.15	4.75	[22]
	3.9	8.90	3.20	4.60	[262]
		9.00	3.50	4.40	[263,25]
	3.9	9.00	3.00	4.90	[136]
SiN	7.5	5.00	2.00	1.90	[260]
	7.6	5.00 - 5.30	2.40	1.50 - 1.80	[261]
	7.9	5.30	2.40	1.80	[22]
	7.0	5.10	2.00	2.00	[262]
		5.30	2.40	1.80	[263,25]
	7.5	5.00	2.00	1.90	[136]
TaO	25.0	4.40	1.40	1.90	[260,136]
	23.0 - 25.0	4.40	0.30	3.00	[261]
	25.0	4.40	0.36	2.94	[22,25]
	26.0	4.50	1.00-1.50	1.90 - 2.40	[262]
		4.40	0.36	2.94	[263]
TiO	40.0	3.50	1.10	1.30	[260,136]
	39.0-110.0	3.00-3.27	0.00	1.90 - 1.97	[261]
	80.0-170.0	3.05	0.00	1.95	[22]
	80.0	3.50	1.20	1.20	[262]
		3.05	0.00	1.95	[263]
AlO	9.0	8.70	2.80	4.80	[262]
	8.0 - 9.0	8.8-9.00	2.78-2.80	4.92 - 5.10	[261]
	9.5-12.0	8.8	2.80	4.90	[22]
		8.80	2.80	4.90	[263]
	10.0	8.80	2.80	4.90	[25]
ZrO	23.0	5.80	1.40	3.30	[25]
	25.0	7.80	1.40	5.30	[260,262]
	22.0 - 25.0	5.00 - 5.80	1.40	2.50 - 3.30	[261]
	12.0-16.0	5.70-5.80	1.40-1.50	3.10 - 3.30	[22]
		5.80	2.50	2.20	[263]
HfO	25.0	5.70	1.50	3.10	[260,262]
	22.0 - 40.0	6.00	1.50	3.50	[261]
	16.0-30.0	4.50-6.00	1.50	1.90 - 3.40	[22]
		6.00	1.50	3.40	[263]
	20.0	6.00	1.50	3.40	[25]
YO	15.0	5.60	2.30	2.20	[262]
	11.3 - 18.0	5.50-6.00	1.30	3.10 - 3.60	[261]
	4.4	6.00	1.30	3.60	[263]
	15.0	6.00	2.30	2.60	[25]
ZrSiO	12.6	6.00	1.50	3.40	[261]
		4.50	0.70	2.70	[22]
	3.8	6.00	1.50	3.40	[263]
		6.00	1.50	3.40	[25]

**Figure 5.19:** Trade-off between electron barrier height (left) or hole barrier height (right) and the permittivity of various dielectric materials.
$\includegraphics[width=.48\linewidth]{figures/tradeoff_e}$ $\includegraphics[width=.48\linewidth]{figures/tradeoff_h}$

**Figure 5.20:** Conduction and valence band edges of various dielectric materials compared to silicon.
$\includegraphics[width=.72\linewidth]{figures/highKbands}$

Choosing the highlighted material parameters from Table 5.1 the gate current density can be computed as a function of the gate bias. It is commonly assumed that an underlying layer of SiO cannot be avoided -- or is even deliberately introduced to achieve a lower trap density at the interface to silicon. Thus, an underlying SiO layer with a thickness of 0.5nm was assumed. The thickness of the high- $\kappa$ layer was adjusted so that the effective oxide thickness (EOT) remains unchanged at 1nm. The gate current density is shown in the left part of Fig. 5.21 as a function of the gate bias for different material combinations. The commonly assumed limit of 1Acm $^{-2}$ gate leakage is also indicated. Both SiO and SiN show a much too high leakage, while TaO, ZrO, and HfO stay below 1Acm $^{-2}$ at $V_\mathrm{GS}$ =1V. Due to the low conduction band offset, TiO shows an especially pronounced current increase for positive gate bias.

To assess the material parameters necessary to reach a specific maximum gate current density the gate current has been calculated as a function of the conduction band offset and dielectric permittivity as shown in the right part of Fig. 5.21. Since it is often not possible to vary the thickness of the underlying SiO layer it was again fixed at 0.5nm and the high- $\kappa$ thickness was adjusted to reach an EOT of 1.5nm. The gate current density was evaluated at a fixed bias point of $V_\mathrm{GS}$ =1.5V and $V_\mathrm{DS}$ =0V. The current density decreases strongly with increasing conduction band offset. Increasing the value of the dielectric permittivity $\kappa$ also strongly reduces the leakage current due to the higher physical stack thickness. However, materials with a conduction band offset below 1eV never reach acceptable gate current densities.

**Figure 5.21:** Gate current density as a function of the gate voltage for different materials. The dielectric stack consists of a 0.5 nm SiO layer and a high- $\kappa$ layer with a total EOT of 1.0 nm (left). Dependence of the gate current on the high- $\kappa$ conduction band offset and dielectric permittivity of a stack with EOT=1.5 nm, a 0.5 nm SiO interface layer at a gate bias of 1.5 V (right).
$\includegraphics[width=.48\linewidth]{figures/layeredBarrierIgVg}$ $\includegraphics[width=.48\linewidth]{figures/barrierDependency}$

It may be asked which thickness of the high- $\kappa$ layer is necessary to achieve a certain gate current density. In the left part of Fig. 5.22 the gate current density is shown for an effective oxide thickness ranging from 0.5nm to 2.0nm as a function of the high- $\kappa$ layer thickness. Again, the stack consists of an underlying 0.5nm layer of SiO and the simulations are performed at a fixed bias point of $V_\mathrm{GS}$ =1.5V and $V_\mathrm{DS}$ =0V. In this plot the curves are only drawn for an EOT of 0.5nm - 2.0nm, and conduction band offsets of $\ensuremath {\mathrm{q}}\ensuremath{\Phi_\mathrm{e}}=1$ eV to $\ensuremath {\mathrm{q}}\ensuremath{\Phi_\mathrm{e}}=3$ eV have been considered. For a conduction band offset of 1eV, large high- $\kappa$ thicknesses are necessary to reduce the leakage. Such large stacks may pose problems due to fringing fields from the drain contact which reduce the threshold voltage of the device.

The tradeoff between the dielectric permittivity and the conduction band offset gives rise to further effects as shown in the right part of Fig. 5.22. If the EOT has to be held at a fixed value, an increase of the SiO layer thickness causes a reduced thickness of the high- $\kappa$ layer. This is shown for different values of the permittivity ( $\kappa=8.0$ - $\kappa=24.0$ ). So, the total stack thickness may be larger than 8nm for $\kappa=24$ , or as small as 1.5nm if only SiO is used. Such a reduction of the total stack thickness, however, has no clear effect on the leakage. It may cause the gate current density at a specific bias point to stay constant, increase, or even decrease depending on the material parameters. For example, the gate leakage for a material with $\kappa=24$ and a conduction band offset of 1eV shows the maximum leakage at a SiO layer thickness of approximately 0.8nm. Therefore, a clear statement about the optimum thickness of the interface layer obviously depends on the material parameters.

**Figure 5.22:** Dependence of the gate current on the high- $\kappa$ layer thickness, conduction band offset, and permittivity of a stack with EOT=2.0 nm and a 0.5 nm SiO interface layer at a gate bias of 1.5 V (left). Dependence of the gate current on the interface layer thickness, conduction band offset, and permittivity of a stack with EOT=1.5 nm at a gate bias of 1.5 V (right).
$\includegraphics[width=.49\linewidth]{figures/tHkDependency}$ $\includegraphics[width=.49\linewidth]{figures/stepTsio2}$

A. Gehring: Simulation of Tunneling in Semiconductor Devices


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